Staff/ Senior Staff Engineer, STA
Renesas · Posted Oct 22
Semiconductor solutions for automotive, industrial, infrastructure, and IoT industries
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About the role
Renesas is a global semiconductor company focused on automotive, industrial, cloud, and IoT innovation, with a growing India presence. The VLSI design team works on advanced semiconductor technologies and high-performance, power-efficient SoCs. This role drives block-level and full-chip timing closure and signoff readiness, developing timing constraints and collaborating with RTL, synthesis, CTS, and physical design teams.
What you will do
- Perform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments.
- Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
- Develop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness.
- Partner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals.
- Drive timing closure through ECO implementation, timing optimization, and timing convergence activities.
- Perform pre-layout and post-layout timing analysis and support tapeout signoff requirements.
- Analyze timing impact due to process, voltage, and temperature (PVT) variations and variation-aware methodologies.
- Review and validate timing exceptions including false paths, multicycle paths, case analysis, and clock definitions.
- Identify root causes of timing violations and recommend effective optimization strategies.
- Participate in cross-functional design reviews and provide guidance on timing-related issues.
- Generate timing reports, closure metrics, and signoff summaries for project stakeholders.
- Support design quality improvements by establishing and enhancing STA methodologies, automation, and best practices.
Skills used in this role
What the employer is looking for
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.
- 7 to 13 years of hands-on experience in Static Timing Analysis (STA) and timing closure for block-level and/or full-chip semiconductor designs.
- Strong understanding of CMOS fundamentals, timing concepts, and end-to-end semiconductor design flow.
- Solid experience with setup/hold analysis, path-based analysis (PBA), and timing signoff methodologies.
- In-depth knowledge of OCV, AOCV, POCV, timing derates, uncertainty modeling, and MMMC analysis.
- Strong understanding of clock tree concepts including clock latency, skew, jitter, uncertainty, and clock propagation.
- Experience developing and debugging timing constraints and timing exceptions.
- Good understanding of SDC syntax, false paths, multicycle paths, generated clocks, and case analysis.
- Hands-on experience with timing closure techniques and ECO methodologies.
- Proficiency with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus.
- Good scripting and automation skills using Tcl, Perl, Python, or similar languages.
- Strong analytical, debugging, and problem-solving skills with the ability to independently resolve complex timing issues.
- Excellent communication and collaboration skills in cross-functional engineering environments.
Preferred qualifications
- Experience with low-power timing analysis and UPF/CPF-aware STA methodologies.
- Familiarity with signal integrity (SI)-aware timing analysis, crosstalk analysis, and IR-drop-aware timing closure.
- Understanding of advanced technology nodes and variation-aware signoff methodologies.
- Exposure to automation, flow development, and methodology enhancement.
- Experience collaborating with Physical Design, RTL, Verification, DFT, and Signoff teams.
- Knowledge of advanced timing signoff practices for high-performance and low-power SoCs.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Renesas
Renesas Electronics Corporation is a global semiconductor manufacturer that designs and supplies advanced embedded processors, microcontrollers, analog, power, and connectivity solutions. Serving the automotive, industrial, infrastructure, and IoT sectors, the company delivers integrated technology to support smarter and more sustainable applications worldwide.
- Industry
- Semiconductors
- Company size
- 21629 employees
- Founded
- 2002-11-01
- Location
- Tokyo, Japan
- Funding stage
- Public Company
Leadership
Representative Executive Officer, President and CEO
Shuhei Shinkai
CFO
Vivek Bhan
Senior Vice President and Chief Technology Officer, Head of Engineering
Stephen Limoges
Senior Vice President and Chief Sales Officer
Utae Nakanishi
CHRO
Recent coverage
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