Staff Digital Verification Engineer
Renesas · Posted Oct 16
Semiconductor solutions for automotive, industrial, infrastructure, and IoT industries
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About the role
Renesas develops complex power management SoCs that integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications. The role sits within a semiconductor verification team working alongside architecture, RTL design, firmware, analog, validation, and systems engineers. This Staff Digital Design Verification Engineer will independently own verification of significant blocks and features from planning through coverage closure, combining hands-on UVM development, coverage-driven verification, and complex debug.
What you will do
- Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
- Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
- Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
- Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
- Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
- Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.
- Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.
- Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.
Skills used in this role
What the employer is looking for
- Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
- 7 or more years of relevant digital design verification experience, or equivalent directly applicable experience.
- Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure.
- Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.
- Experience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria.
- Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures.
- Strong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues.
- Working knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings.
- Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.
- Ability to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams.
- Strong technical ownership and a disciplined approach to verification completeness.
- Ability to reason beyond directed requirements and identify meaningful corner cases and feature interactions.
- Clear communication of technical risk, progress, and signoff evidence.
- A collaborative mindset and interest in improving verification methodology and productivity.
Preferred qualifications
- Experience verifying complex SoCs, power management ICs, voltage regulators, digital controllers, or mixed-signal products.
- Experience verifying RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled hardware features.
- Familiarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols.
- Understanding of telemetry, fault and alert handling, power sequencing, multiphase regulation, or digital control loops.
- Experience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or comparable tools.
- Experience with formal verification, gate-level simulation, silicon bring-up, or pre-silicon-to-silicon correlation.
- Experience improving regression infrastructure, coverage analytics, failure triage, or verification automation.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Renesas
Renesas Electronics Corporation is a global semiconductor manufacturer that designs and supplies advanced embedded processors, microcontrollers, analog, power, and connectivity solutions. Serving the automotive, industrial, infrastructure, and IoT sectors, the company delivers integrated technology to support smarter and more sustainable applications worldwide.
- Industry
- Semiconductors
- Company size
- 21629 employees
- Founded
- 2002-11-01
- Location
- Tokyo, Japan
- Funding stage
- Public Company
Leadership
Representative Executive Officer, President and CEO
Shuhei Shinkai
CFO
Vivek Bhan
Senior Vice President and Chief Technology Officer, Head of Engineering
Stephen Limoges
Senior Vice President and Chief Sales Officer
Utae Nakanishi
CHRO
Recent coverage
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