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Staff CAD Layout Automation and Methodology Engineer

Renesas · Posted Nov 5

Semiconductor solutions for automotive, industrial, infrastructure, and IoT industries

Bengaluru, KA, IndiaFull-timeOnsiteLead/Staff8+ years₹40.0L–₹65.0L yearly39 applicants
SemiconductorsManufacturingEmbedded ProcessingAutomotiveIoTPublic Company
Full time

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About the role

The PDK team at Renesas develops and supports process design kit physical design components and methodologies for analog, mixed-signal, and digital design teams across mature and advanced technology nodes. The role focuses on building, integrating, and releasing PDK physical design flows, layout structures, and design enablement collateral. The engineer will define physical-design methodologies and collaborate with foundries, EDA vendors, PDK teams, and IC design teams.

What you will do

  • Develop, adapt, enhance and release PDK Physical Design flows and design enablement collateral for internal customers.
  • Define and maintain physical-design methodologies, configurations and customization options for technology and product-specific requirements.
  • Develop and maintain technology-dependent layout structures, reference components and supporting utilities.
  • Translate foundry technology requirements into robust and reusable PDK Physical Design flows and solutions.
  • Collaborate with foundries, EDA vendors, PDK and design teams to address physical-design requirements and integration.

Skills used in this role

What the employer is looking for

  • Good knowledge of CMOS , planar and finfet fundamentals, semiconductor technology and IC design, with a background in Electrical/Electronics Engineering, Semiconductor Physics or a related discipline.
  • Strong understanding of IC physical design and layout methodologies, including technology-dependent layout requirements, chip-level integration and Tape-Out considerations.
  • Demonstrable experience in developing, integrating and maintaining tools , flows for Physical design using Virtuoso environment
  • Strong debugging and problem-solving skills across layout, EDA and design-flow environments.
  • Ability to interpret foundry technology documentation and design requirements and translate them into flows using native EDA vendor tools or custom tools
  • Good knowledge of UNIX/Linux environments, shell scripting, with proficiency in Python, Perl
  • Strong Cadence SKILL programming experience
  • Good communication and collaboration skills for working with foundries, EDA vendors, CAD/EDA teams and IC design teams.
  • Experience developing automation and productivity tools for supporting design teams is highly desirable.
  • Background in Full chip layout/physical design development and Tapeout is highly desired

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Renesas

Renesas Electronics Corporation is a global semiconductor manufacturer that designs and supplies advanced embedded processors, microcontrollers, analog, power, and connectivity solutions. Serving the automotive, industrial, infrastructure, and IoT sectors, the company delivers integrated technology to support smarter and more sustainable applications worldwide.

Industry
Semiconductors
Company size
21629 employees
Founded
2002-11-01
Location
Tokyo, Japan
Funding stage
Public Company

Leadership

HS
Hidetoshi Shibata

Representative Executive Officer, President and CEO

SS

Shuhei Shinkai

CFO

VB

Vivek Bhan

Senior Vice President and Chief Technology Officer, Head of Engineering

SL

Stephen Limoges

Senior Vice President and Chief Sales Officer

UN

Utae Nakanishi

CHRO

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