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Sr Manager - DFT

AMD · Posted Oct 22

High-performance processors, graphics cards, data center solutions, and AI accelerators

Bangalore, IndiaFull-timeOnsiteLead/Staff15+ years₹65.0L–₹1.1Cr yearly<25 applicants
SemiconductorsHardwareArtificial IntelligenceCloud ComputingGamingPublic Company
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About the role

The S3 SoC DFT Team at AMD is responsible for advanced DFT architecture, design, integration, verification, and silicon enablement across complex SoCs. This role provides technical and people leadership for a team of DFT engineers and works closely with DFT Architecture, RTL Design, Verification, Physical Design, STA, Test, and Post-Silicon teams. The Senior Manager will own DFT execution across multiple programs and drive scalable, robust DFT solutions from requirements through silicon bring-up.

What you will do

  • Lead and manage a team of DFT engineers responsible for end-to-end DFT design, integration, verification, and implementation.
  • Provide technical leadership for complex DFT architectures including Scan, ATPG, MBIST, Boundary Scan/JTAG and related test methodologies.
  • Own DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up.
  • Partner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs.
  • Drive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution.
  • Work closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges.
  • Lead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug.
  • Drive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables.
  • Develop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality.
  • Provide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues.
  • Build and develop engineering talent through mentoring, technical guidance, and capability development.
  • Collaborate effectively with geographically distributed engineering teams and stakeholders.

Skills used in this role

DFTScanATPGMBISTBoundary ScanJTAGASICSoCRTLVerilogSystemVerilogSiemens TessentSynopsys Design CompilerSpyGlassStatic Timing AnalysisCDCLintSynthesisSimulationPerlPythonTclLow-Power DesignLeadershipCommunication

What the employer is looking for

  • B.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
  • Typically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership.

Preferred qualifications

  • Extensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation.
  • Strong experience leading end-to-end DFT execution for complex, high-performance SoCs.
  • Demonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs.
  • Deep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture.
  • Strong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools.
  • Experience defining and developing scalable DFT flows and methodologies.
  • Strong knowledge of RTL development and integration using Verilog/SystemVerilog.
  • Experience integrating multiple IPs and DFT structures into large and complex SoCs.
  • Good understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies.
  • Strong understanding of Static Timing Analysis, DFT timing constraints and timing closure.
  • Experience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization.
  • Excellent hands-on debugging skills with the ability to drive complex technical issues to closure.
  • Strong scripting and automation experience using Perl, Python and TCL.
  • Understanding of low-power design concepts including clock gating and power gating.
  • Experience with post-silicon bring-up and silicon DFT/debug is highly desirable.
  • Strong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams.
  • Proven ability to balance technical depth, people leadership, program execution, and strategic priorities.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About AMD

AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.

Industry
Semiconductors
Company size
31000 employees
Founded
1969-05-01
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company

  • 2007-11-16Post Ipo

Leadership

DL
Dr. Lisa Su

Chair and Chief Executive Officer

JH
Jean Hu

Executive Vice President, Chief Financial Officer and Treasurer

MP
Mark Papermaster

Executive Vice President and Chief Technology Officer

PG
Philip Guido

Executive Vice President and Chief Commercial Officer

FN
Forrest Norrod

Executive Vice President and General Manager, Data Center Solutions Business Group

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