SoC DFT Technical Manager, Google Cloud
Google · Posted Nov 3
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About the role
The AI and Infrastructure team builds AI and hyperscale infrastructure at Google, including custom silicon such as TPUs, Vertex AI for Google Cloud, Google Global Networking, and data center operations. The role sits within TPU hardware development, focused on DFT architecture and verification of complex digital designs for AI/ML-driven systems. This manager will define DFT architecture for multi-core SoCs and lead the DFT lifecycle from RTL planning through post-silicon validation and production release.
What you will do
- Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
- Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
- Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
- Collaborate with post silicon team, Physical Design and Power Architects.
- Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.
Skills used in this role
What the employer is looking for
- Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
- 10 years of experience in SoC DFT architecture and design.
- 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
- 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
- 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
- Experience in Tcl, Python, or Perl for developing automation flows.
Preferred qualifications
- PhD in Electrical Engineering with a focus on VLSI testing, fault tolerance, or reliability.
- Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.
- Experience managing global technical teams and driving vendor engagement.
- Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Google
Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.
- Industry
- Internet
- Company size
- 180000+ employees
- Founded
- 1998-09-04
- Location
- Mountain View, California, USA
- Funding stage
- Public Company
Funding
Public Company · $25M raised
- 1999-06-07Series A$25M
Leadership
Chief Executive Officer
Senior Vice President and Chief Financial Officer
Senior Vice President and Chief Business Officer
Chief Executive Officer, Google Cloud
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