SoC Constraints Design Engineer, Silicon
Google · Posted Oct 28
Search engine, cloud computing, software, hardware, and artificial intelligence services
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About the role
Google Silicon develops custom silicon solutions for Google's direct-to-consumer products, including Pixel and other devices, combining Google AI, software, and hardware. The Platforms and Devices team spans computing software platforms, first-party devices, and services. This role will drive SoC design constraints development and validation, timing analysis flows, and sign-off timing convergence with architecture, RTL, and implementation teams.
What you will do
- Collaborate with Architecture/Microarchitecture/ Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence.
- Lead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation.
- Understand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes.
- Design constraints validation across multiple corners/modes using Fishtail/Timevision.
- Work closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.
Skills used in this role
What the employer is looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts.
- 1 year of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology scaling and Process Design Kit (PDK) changes.
- Experience with scripting languages (e.g., Python, Perl, Tcl) to automate workflows, parse electronic design automation (EDA) reports, and develop custom utilities.
Preferred qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience in developing constraints and validating the same using Timing Constraints Manager (e.g., Synopsys)/TimeVision (e.g., Ausdia).
- Experience with liberty timing models and Static Timing Analysis tools (e.g., TCM/TimeVision, Primetime, Tempus).
- Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.
- Understanding of various external Input/Output (IO) protocols.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Google
Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.
- Industry
- Internet
- Company size
- 180000+ employees
- Founded
- 1998-09-04
- Location
- Mountain View, California, USA
- Funding stage
- Public Company
Funding
Public Company · $25M raised
- 1999-06-07Series A$25M
Leadership
Chief Executive Officer
Senior Vice President and Chief Financial Officer
Senior Vice President and Chief Business Officer
Chief Executive Officer, Google Cloud
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