Silicon Engineer, Custom Circuits and SRAM, Google Cloud
Google · Posted Sep 18
Search engine, cloud computing, software, hardware, and artificial intelligence services
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About the role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide, with your expertise shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will work to shape the future of AI/ML hardware acceleration, driving cutting-edge TPU (Tensor Processing Unit) technology and verifying complex digital designs with a specific focus on TPU architecture and its integration within AI/ML driven systems.
What you will do
- Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits.
- Drive proper IP integration and margins with the physical design team.
- Work with the foundry, IP partners, and the technology, physical design, and architecture teams in advanced CMOS nodes to optimize our products for PPA, schedule, and reliability.
- Drive and support test chip design, execution, and validation of critical circuit IPs.
- Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
- Drive development of a leading edge technology platform for custom, high performance ASIC's and SoC's, from design through manufacturing, packaging, and test.
Skills used in this role
What the employer is looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, including nodes (e.g., 7nm or below).
- Experience with SPICE and transistor level design in nodes.
- Experience with concurrent optimization across custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
- Experience in CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics, and in scripting or automation in one or more programming languages (e.g., Tcl, Python, or Perl).
Preferred qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with scripting languages such as Perl, Python, or Tcl.
- Experience working with foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.
- Understanding of collaterals for front-end and back-end design teams.
- Track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout.
- Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
- Strong documentation and presentation skills to communicate efficiently with teammates and vendors/partners.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Google
Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.
- Industry
- Internet
- Company size
- 180000+ employees
- Founded
- 1998-09-04
- Location
- Mountain View, California, USA
- Funding stage
- Public Company
Funding
Public Company · $25M raised
- 1999-06-07Series A$25M
Leadership
Chief Executive Officer
Senior Vice President and Chief Financial Officer
Senior Vice President and Chief Business Officer
Chief Executive Officer, Google Cloud
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