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Senior Staff / Principal Engineer – SoC Physical Design

Qualcomm · Posted Oct 11

Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions

Bangalore, IndiaFull-timeOnsiteLead/Staff15+ years₹80.0L–₹1.5Cr yearly26 applicants
SemiconductorsWireless TechnologyTelecommunicationsArtificial IntelligenceMobile ComputingPublic Company
Full time

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About the role

Qualcomm's Hardware Engineering Group plans, designs, optimizes, verifies, and tests electronic systems, circuits, and digital/analog/RF/optical systems that launch cutting-edge, world-class products, collaborating cross-functionally to meet performance requirements. This senior staff/principal role leads end-to-end physical design implementation for large-scale SoCs and complex subsystems, owning floorplanning, power planning, placement, CTS, routing, timing closure, signal integrity, and physical verification. The position drives PPA optimization and signoff closure on advanced nodes, defines physical design methodologies and automation flows, and provides technical leadership and mentoring through tapeout.

What you will do

  • Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.
  • Own full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.
  • Drive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.
  • Define and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.
  • Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.
  • Resolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.
  • Provide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.
  • Mentor and guide junior engineers, driving technical excellence across the organization.
  • Influence future design methodologies and contribute to strategic technology roadmap decisions.

Skills used in this role

ASICSoCPhysical DesignFloorplanningPower Delivery NetworkPlacementCTSRoutingTiming ClosureSignal IntegrityIR/EM AnalysisPhysical VerificationSTADRC/LVSInnovusICC2Fusion CompilerPrimeTimeTempusCalibreRedHawkVoltusLow-Power Design5nm3nm

What the employer is looking for

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • 15+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.
  • Deep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.
  • Strong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.
  • Extensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.
  • Proven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).
  • Strong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.
  • Demonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.
  • Excellent leadership, communication, and stakeholder management skills.

Preferred qualifications

  • Experience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.
  • Demonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.
  • Experience driving methodology development, flow automation, and design productivity improvements.
  • Prior experience leading and mentoring teams of Physical Design engineers.
  • Candidates from leading semiconductor product companies are strongly preferred.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Qualcomm

Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.

Industry
Semiconductors
Company size
50000+ employees
Founded
1985
Location
San Diego, California, USA
Funding stage
Public Company

Funding

Public Company · $53M raised

Western Technology Investment
  • 2018-11-01Grant

Leadership

CR
Cristiano R. Amon

President and Chief Executive Officer

AP
Akash Palkhiwala

Chief Financial Officer and Chief Operating Officer

JH

James H. Thompson

Chief Technology Officer

DM
Don McGuire

Chief Marketing Officer

AC

Ann Chaplin

General Counsel and Corporate Secretary