Senior Staff Engineer, Physical Design
Renesas · Posted Oct 22
Semiconductor solutions for automotive, industrial, infrastructure, and IoT industries
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About the role
Renesas India is focused on growing the India market by creating SoCs, software, power, and analog chips for local needs. The role sits in physical design for advanced-node, complex hierarchical SoCs, leading subsystem- and block-level implementation and closure. It works closely with SoC-level physical design, RTL, STA, power, verification, and backend teams to align clocking, floorplanning, and integration.
What you will do
- Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
- Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
- Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
- Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
- Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
- Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
- Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions
Skills used in this role
What the employer is looking for
- 7+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs
- Strong expertise in:
- Timing closure and constraint management
- Congestion analysis and resolution
- Power integrity and power-aware physical implementation
- Block and subsystem-level physical design flows
- Solid understanding of SoC-level floorplanning and clocking methodologies, including:
- Clock domain partitioning
- Clock tree architecture
- Skew management
- Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)
- Hands-on experience with industry-standard tools such as:
- Synopsys ICC2, Fusion Compiler, PrimeTime
- Cadence Innovus, Tempus, Certus
- Signoff and analysis platforms
- Proficiency in scripting and automation using Tcl, Python, and/or Perl
- Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams
- Strong understanding of low-power design techniques and power-aware implementation methodologies
- BTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field
Benefits and support
- Compensation and benefits are detailed in the job posting
About Renesas
Renesas Electronics Corporation is a global semiconductor manufacturer that designs and supplies advanced embedded processors, microcontrollers, analog, power, and connectivity solutions. Serving the automotive, industrial, infrastructure, and IoT sectors, the company delivers integrated technology to support smarter and more sustainable applications worldwide.
- Industry
- Semiconductors
- Company size
- 21629 employees
- Founded
- 2002-11-01
- Location
- Tokyo, Japan
- Funding stage
- Public Company
Leadership
Representative Executive Officer, President and CEO
Shuhei Shinkai
CFO
Vivek Bhan
Senior Vice President and Chief Technology Officer, Head of Engineering
Stephen Limoges
Senior Vice President and Chief Sales Officer
Utae Nakanishi
CHRO
Recent coverage
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