Senior STA Engineer
Samsung Semiconductor · Posted Oct 6
Advanced memory, foundry, system LSI, and semiconductor manufacturing solutions
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About the role
Samsung Semiconductor India Research (SSIR) is one of the largest Samsung Electronics R&D centers outside Korea, working on industry-leading semiconductor solutions across System LSI, Memory and Foundry, including Foundation IP Design, Mobile SoCs, storage solutions, AI/ML, 5G/6G, neural processors and multimedia IPs. The role is an ASIC design engineering position with emphasis on synthesis, timing closure, low power, and place and route. The engineer will develop constraints, run synthesis, drive timing and equivalence closure with RTL, physical design and low power teams, and mentor junior engineers.
What you will do
- Develop constraints, run synthesis, perform low power, timing and equivalence checks and closure
- Work closely with RTL designer, physical design, low power teams to optimize performance, area and power
- Generate, review and validate design constraints to achieve timing closure of high speed design
- Develop floor-planning and CTS guidelines for layout
- Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure
- Perform in-house quality check before P&R and after P&R
- Constraint management tool and Verilog coding experience
- Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
- Improve existing process and enhance team work efficiency
Skills used in this role
What the employer is looking for
- BSEE or MSEE in EE with 4+ years of relevant experience in the following areas
- Must be hands-on technical expert
- Strong written and oral communication skills
- Good understanding of Deep Sub Micron topics and their associated issues
- Good Experience in Top/Block DCT/DCG based Synthesis, Equivalence checks
- Experience in leading Hard-IP/HardBlocks/SOC timing closure with deep technical knowledge in all
- Should be able to comprehend architecture and associated limitations with respect to synthesis and STA perspective and be able to predict the schedule, amount of task and personnel involved
- Good experience with functional and test mode constraints and developing IOs and IP constraints, optimization, STA setup with associated automation, cross-talk noise/delay, STA signoff, GCA, VCLP
- Good understanding of Low Power Management and experience with its implication on synthesis and STA
- Should have ability to develop good understanding of a design and associated IPs
- Very good in understanding and defining constraints and critical high speed path timing closure working with BE teams
- Perl/Tcl scripting is required
- Good understanding of the APR flows is desired
- Experience – 4 to 15 Years
- B.Tech/B.E/M.Tech/M.E
Benefits and support
- Compensation and benefits are detailed in the job posting
About Samsung Semiconductor
Samsung Semiconductor is a world leader in advanced memory technology, integrated circuits, and semiconductor foundry services. Part of Samsung Electronics, the company develops essential hardware components like DRAM, NAND flash, application processors, and sensor solutions that power global computing, mobile, and AI infrastructure. Through continuous innovation in lithography and packaging, Samsung drives technological advancements across consumer electronics and enterprise data centers.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1969
- Location
- San Jose, California, USA
- Funding stage
- Public Company
Leadership
Jinman Han
President of Foundry Business
Yong-In Park
President of System LSI Business
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