Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation
Google · Posted Oct 15
Search engine, cloud computing, software, hardware, and artificial intelligence services
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About the role
The AI and Infrastructure team delivers Google's hyperscale computing platforms — including TPUs, Vertex AI for Google Cloud, Google Global Networking, and data center operations — serving Googlers, Google Cloud customers, and billions of Google users. The role sits on a team developing custom silicon for AI/ML hardware acceleration and ASICs used to improve traffic efficiency in data centers. This engineer will work on HBM memory subsystem design, integration, and validation: microarchitecture and RTL for memory controller frontends and backends, HBM/DDR PHY macro integration, and post-silicon bring-up and characterization for next-generation data center accelerators.
What you will do
- Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing, and configurability for multi-channel and pseudo-channel configurations.
- Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure (DFI pipe wrappers, clock/reset, PLL references, sideband bridging) and schedule from concept to tapeout.
- Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection), while tracking JEDEC specs and memory conferences for the latest HBM trends.
- Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT (process, voltage, temperature) corners.
- Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug.
Skills used in this role
Preferred qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience delivering configurable, reusable IP-parameterization, release packaging, integration guides and customer-facing documentation.
- Experience integrating third-party controller and PHY IP (Rambus, Cadence/Synopsys class) into production silicon.
- Experience with SECDED per pseudo-channel, Reed–Solomon symbol correction, error queues, lane/row repair, address-folded CRC.
- Experience with UVM methodology and emulation-based pre-silicon validation, and familiarity with memory telemetry and Silicon Lifecycle Management (SLM) — per-pseudo-channel counters, link availability, continuous eye-opening monitors.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Google
Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.
- Industry
- Internet
- Company size
- 180000+ employees
- Founded
- 1998-09-04
- Location
- Mountain View, California, USA
- Funding stage
- Public Company
Funding
Public Company · $25M raised
- 1999-06-07Series A$25M
Leadership
Chief Executive Officer
Senior Vice President and Chief Financial Officer
Senior Vice President and Chief Business Officer
Chief Executive Officer, Google Cloud
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