Senior Physical Design Engineer
Samsung Semiconductor · Posted Oct 12
Advanced memory, foundry, system LSI, and semiconductor manufacturing solutions
Get a personal compatibility score
Add a resume for personal matches
About the role
Samsung Semiconductor India Research (SSIR) is one of the largest Samsung Electronics R&D centers outside Korea, delivering semiconductor solutions across System LSI, Memory and Foundry and working on technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/6G, neural processors, serial interfaces and multimedia IPs. This role drives complex SOC top-level physical implementation for next-generation SOCs in mobile application processors, modem sub-systems and connectivity chips through synthesis, place and route, STA, and timing and physical signoffs. The engineer will also work on timing closure of complex blocks and full-chip designs, top-level floor planning, and PPA optimization on deep sub-micron nodes.
What you will do
- Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs
Skills used in this role
What the employer is looking for
- Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.
- Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.
- Should have strong understanding of timing, power and area trade-offs and optimization of PPA.
- Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities.
- Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1 GHZ.
- Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking.
- Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).
- Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.
- Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
- Should have gone through recent successful SOC tape-outs.
- Experience – 5 to 20 Years
- B.Tech/B.E/M.Tech/M.E
Benefits and support
- Compensation and benefits are detailed in the job posting
About Samsung Semiconductor
Samsung Semiconductor is a world leader in advanced memory technology, integrated circuits, and semiconductor foundry services. Part of Samsung Electronics, the company develops essential hardware components like DRAM, NAND flash, application processors, and sensor solutions that power global computing, mobile, and AI infrastructure. Through continuous innovation in lithography and packaging, Samsung drives technological advancements across consumer electronics and enterprise data centers.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1969
- Location
- San Jose, California, USA
- Funding stage
- Public Company
Leadership
Jinman Han
President of Foundry Business
Yong-In Park
President of System LSI Business
Recent coverage
SammyGuru
Samsung reveals plans for its Yongin semiconductor complex2026-10-05
Samsung Semiconductor Newsroom
Samsung Electronics and ASML Expand Strategic Collaboration for Next-Generation Semiconductor Manufacturing2026-09-08
Samsung Semiconductor Newsroom
Samsung Unveils Next-Gen 3D-Memory Vision at FMS 20262026-08-05
Samsung Semiconductor Newsroom
Samsung Electronics and Broadcom Expand Strategic Collaboration Across Memory and Foundry Technologies2026-07-25