Senior Engineer, SoC PnP Architect
Arm · Posted Nov 3
Semiconductor IP, energy-efficient CPU architecture, and high-performance compute platforms
Bengaluru, IndiaFull-timeHybridSenior Level4+ years₹40.0L–₹65.0L yearly32 applicants
SemiconductorsChip DesignIP LicensingArtificial IntelligenceCloud ComputingPublic Company
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About the role
Arm's SoC PnP Architecture role focuses on system-level performance, power, and efficiency investigations across complex silicon platforms. The work spans pre-silicon performance analysis and modeling, emulation, post-silicon characterization, and architecture tradeoff analysis for SoC infrastructure including interconnect, memory, IO, and power management. This senior engineer will develop and correlate performance/power models, debug bottlenecks, and translate findings into architectural recommendations.
What you will do
- Design, build, and maintain systems that power Arm's semiconductors platform
- Collaborate with cross-functional teams to ship high-impact features
Skills used in this role
What the employer is looking for
- 4+ years of experience in SoC PnP Architecture within the semiconductor industry, with a strong track record of driving system-level performance, power, and efficiency investigations across complex silicon platforms.
- Strong expertise in SoC performance architecture and pre-silicon performance analysis , including:
- Hands-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent
- Performance analysis using cycle-accurate, transaction-level, and emulation-based environments
- Waveform-based debug and signal-level performance analysis
- Latency, bandwidth, throughput, QoS, and utilization characterization
- Transaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols
- Identification of system-level bottlenecks across compute, interconnect, memory, and IO subsystems
- Architectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity
- Strong experience with SOC Performance and Power modeling methodologies , including:
- Development and use of SystemC/TLM, analytical, trace-driven architecture models
- Building and calibrating models for performance, power, latency, bandwidth, utilization, and efficiency analysis
- Model-to-silicon correlation , including alignment of pre-silicon projections, emulation results, and post-silicon measurements
- Early-stage architecture exploration to evaluate performance, power, area, thermal, TDP, and efficiency tradeoffs
- Using models to guide SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization
- Ability to translate modeling insights into clear architectural recommendations and measurable product improvements
- Extensive experience in post-silicon performance and power characterization , including:
- Silicon bring-up support from a performance and PnP perspective
- Performance counter, PMU, telemetry, and trace-driven investigations
- Correlation of pre-silicon projections, architectural models, and silicon measurements
- Root-cause analysis of performance gaps, power inefficiencies, and workload-level bottlenecks
- System-level performance tuning under real silicon constraints
- Analysis of workload behavior under power, thermal, voltage, frequency, and TDP limits
- Strong understanding of SoC system infrastructure and platform-level PnP behavior , including:
- Coherent interconnect fabrics and cache-coherency protocols
- DDR memory subsystems, memory controller behavior, scheduling, QoS, and bandwidth efficiency
- IO subsystems including PCIe, CXL
- Power management architecture, DVFS, clocking, voltage domains, power states, and throttling mechanisms
- Proven experience working in both Linux and bare-metal environments , including:
- Performance profiling and debug in Linux-based systems
- Kernel-level performance analysis and tracing using perf, ftrace, PMU-based analysis, or equivalent tools
- Low-level bring-up, debug, and performance characterization in bare-metal environments
- Understanding of boot flows, firmware interactions, BIOS/UEFI or bootloader configuration, and system initialization impacts on performance and power
- Ability to debug issues across hardware, firmware, OS, driver, and workload layers
- Strong background in computer architecture and microarchitecture , including:
- CPU/GPU/NPU/DSP or accelerator performance behavior
- Pipelines, cache hierarchy, prefetching, coherency, memory systems, and interconnect behavior
- System-level performance interactions across compute, memory, IO, and power-management blocks
- Workload characterization and mapping of application behavior to architectural bottlenecks
- Proficiency in C/C++ and Python for developing:
- Performance and power analysis tools
- Automation frameworks
- Profiling and telemetry infrastructure
- Data analysis and visualization dashboards
- Correlation flows across model, emulation, and silicon data
- Excellent communication and cross-functional collaboration skills, with the ability to:
- Clearly present complex performance and power findings to architecture, design, verification, firmware, software, and leadership teams
- Drive data-based architectural recommendations
- Influence SoC architecture, platform configuration, and product-level PnP decisions
- Lead investigations across multiple teams and convert debug findings into architectural improvements, tuning proposals, or product guidance
Benefits and support
- Hybrid working
- Flexible working patterns
About Arm
Arm architects, develops, and licenses high-performance, energy-efficient CPU products and related semiconductor intellectual property. Its technology powers over 99% of the world's smartphones as well as a vast array of devices ranging from tiny sensors and wearables to cloud-scale AI supercomputers.
- Industry
- Semiconductors
- Company size
- 8000+ employees
- Founded
- 1990
- Location
- Cambridge, United Kingdom
- Funding stage
- Public Company
Funding
Public Company
SoftBank GroupSoftBank Vision Fund
- 2023-09-14IPO$5.23B
Leadership
RH
Rene Haas
Chief Executive Officer, Board Member
JC
Jason Child
Executive Vice President and Chief Financial Officer
SC
Spencer Collins
Executive Vice President, Chief Legal Officer and Head of Corporate Development
WA
Will Abbey
Executive Vice President and Chief Commercial Officer
RG
Richard Grisenthwaite
Executive Vice President and Chief Architect
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