Senior Engineer -Low Power CLP
Arm · Posted Sep 29
Semiconductor IP, energy-efficient CPU architecture, and high-performance compute platforms
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About the role
Arm's Solutions Engineering group focuses on delivering quality silicon, ensuring that signoff checks across various domains (including low-power and logical equivalence verification) are diligently performed, and on improvising methodologies and influencing EDA tools. The team validates RTL-to-Gate and Gate-to-GDS implementations, ensures power intent correctness, and enables high-quality silicon tapeout. This role performs low-power structural (CLP/VCLP) verification and LEC signoff for complex SoC and IP designs, and builds automation and methodology for these flows.
What you will do
- Low Power structural check
- Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.
- Verify and validate UPF implementation across RTL, netlist, and physical design stages.
- Perform power-aware equivalence checking and resolve identified issues.
- Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.
- Implement SoC-level low-power structural checks and debug issues through closure.
- Logical Equivalence Checking (LEC/Formality):
- Perform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using Cadence Conformal LEC.
- Analyze, debug, and resolve non-equivalences and aborts across different stages of the design flow.
- Develop, automate, and maintain robust LEC flows and signoff methodologies.
- Drive LEC failure resolution and closure, and generate comprehensive signoff reports.
- Implement and debug SoC-level flat LEC runs through signoff.
- Methodology and Automation:
- Develop TCL, Perl, and Python scripts to automate verification tasks and improve productivity.
- Build and maintain reusable verification flows and debug utilities to improve efficiency and scalability.
- Drive methodology enhancements for low-power verification signoff and efficient resolution of verification aborts.
Skills used in this role
What the employer is looking for
- We are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.
- Strong experience with low-power design and verification, including hands-on knowledge of UPF/CPF and SystemVerilog.
- Hands-on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.
- Experience with Logic Equivalence Checking (LEC) and power-aware LEC, with strong skills in analyzing and resolving verification failures.
- Ability to effectively debug CLP/VCLP and LEC issues and drive them through closure.
- Understanding of synthesis and Place & Route (P&R) flows is an advantage.
- Ability to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Arm
Arm architects, develops, and licenses high-performance, energy-efficient CPU products and related semiconductor intellectual property. Its technology powers over 99% of the world's smartphones as well as a vast array of devices ranging from tiny sensors and wearables to cloud-scale AI supercomputers.
- Industry
- Semiconductors
- Company size
- 8000+ employees
- Founded
- 1990
- Location
- Cambridge, United Kingdom
- Funding stage
- Public Company
Funding
Public Company
- 2023-09-14IPO$5.23B
Leadership
Chief Executive Officer, Board Member
Executive Vice President and Chief Financial Officer
Executive Vice President, Chief Legal Officer and Head of Corporate Development
Executive Vice President and Chief Commercial Officer
Executive Vice President and Chief Architect
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