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Senior DFT Design/Micro architect Engineer, Google Cloud

Google · Posted Nov 6

Search engine, cloud computing, software, hardware, and artificial intelligence services

Bengaluru, Karnataka, IndiaFull-timeOnsiteSenior Level8+ years₹80.0L–₹1.3Cr yearly34 applicants
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About the role

The AI and Infrastructure team builds hardware, software, and networking technologies that power Google services, including custom silicon for TPU-based AI/ML acceleration. The role is focused on DFT architecture and implementation for complex ASICs and SoCs. The Senior DFT Design/Micro architect Engineer will define DFT strategy, insert DFT logic, validate test design rule checks, and support post-silicon debug and production patterns.

What you will do

  • Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed iOs, Analog DFT).
  • Develop and drive die level DFT validation strategy and Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
  • Generate and deliver the production and debug patterns to Post Silicon engineering team and run a diagnosis for post silicon supports.

Skills used in this role

What the employer is looking for

  • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  • 8 years of experience in the implementation and validation of DFT technologies.
  • Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
  • Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
  • Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  • Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
  • Experience in fault modeling.
  • Experience in SoC cycles, silicon bringup, and silicon debug activities.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Google

Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.

Industry
Internet
Company size
180000+ employees
Founded
1998-09-04
Location
Mountain View, California, USA
Funding stage
Public Company

Funding

Public Company · $25M raised

Kleiner PerkinsSequoia Capital
  • 1999-06-07Series A$25M

Leadership

SP
Sundar Pichai

Chief Executive Officer

AA
Anat Ashkenazi

Senior Vice President and Chief Financial Officer

PS
Philipp Schindler

Senior Vice President and Chief Business Officer

TK
Thomas Kurian

Chief Executive Officer, Google Cloud

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