Google logo

Senior DFT Design/Micro Architect Engineer, Google Cloud

Google · Posted Oct 12

Search engine, cloud computing, software, hardware, and artificial intelligence services

Bengaluru, Karnataka, IndiaFull-timeOnsiteSenior Level5–10 years₹45.0L–₹85.0L yearly<25 applicants
InternetCloud ComputingSoftwareHardwareArtificial IntelligenceAdvertisingPublic Company
Be an early applicantFull time

Get a personal compatibility score

Add a resume for personal matches

About the role

The AI and Infrastructure team at Google builds AI and infrastructure at hyperscale, including custom silicon solutions such as TPUs that power Google's most demanding AI/ML applications, along with Vertex AI, Google Global Networking, and data center operations. The team works from low-level circuit design through large system design and on to high-volume manufacturing. This role is a DFT micro-architect/design engineer position focused on DFT strategy and architecture, DFT logic insertion, die-level DFT validation, TDRC closure, and post-silicon test pattern generation and debug for TPU architecture integrated within AI/ML-driven systems.

What you will do

  • Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
  • Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
  • Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Skills used in this role

DFTHierarchical DFTAnalog DFTDie-Level DFT ValidationTest Design Rule Checks (TDRC)Boundary ScanScan ChainsDFT CompressionLogic BISTTAP ControllerClock Control BlockFault ModelingIP IntegrationMulti-Die SoCsSoCSilicon Bring-UpSilicon DebugDigital Design VerificationTPUAI/ML Hardware AccelerationMicroarchitecture

Preferred qualifications

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field.
  • Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
  • Experience in fault modeling.
  • Experience in SoC cycles, silicon bringup, and silicon debug activities.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Google

Google LLC is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. As a subsidiary of Alphabet Inc., it is widely recognized for services like Google Search, YouTube, Android, and the Gemini AI ecosystem.

Industry
Internet
Company size
180000+ employees
Founded
1998-09-04
Location
Mountain View, California, USA
Funding stage
Public Company

Funding

Public Company · $25M raised

Kleiner PerkinsSequoia Capital
  • 1999-06-07Series A$25M

Leadership

SP
Sundar Pichai

Chief Executive Officer

AA
Anat Ashkenazi

Senior Vice President and Chief Financial Officer

PS
Philipp Schindler

Senior Vice President and Chief Business Officer

TK
Thomas Kurian

Chief Executive Officer, Google Cloud