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Senior Analog layout Engineer

AMD · Posted Oct 22

High-performance processors, graphics cards, data center solutions, and AI accelerators

Hyderabad, IndiaFull-timeOnsiteSenior Level8+ years₹40.0L–₹60.0L yearly<25 applicants
SemiconductorsHardwareArtificial IntelligenceCloud ComputingGamingPublic Company
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About the role

AMD's Design Engineering team works on advanced process technology nodes at 7nm and below. The team designs high-performance analog and digital circuits such as ADCs, DACs, PLLs, memory interfaces, references, custom IOs, LDOs, and ESD structures integrated into AMD products. This role is for an experienced analog layout design engineer focused on mixed-signal IC layout, floorplanning, verification, and reliability in advanced CMOS geometries.

What you will do

  • Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience
  • Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage
  • Extensive Floorplanning, power grid and signal flow planning experience
  • Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
  • Excellent understanding of signal and clock shielding and isolation techniques
  • Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects
  • Excellent written and oral communication skills are also required
  • Ability to work well as part of a team
  • Excellent problem solving skills

Skills used in this role

Analog LayoutCMOS7nmCadence VirtuosoMentor CalibreLVSDRCERCANTESDLatch-upEMIRFloorplanningHBMGDDRDDRLPDDRADCDACPLLLDOCustom I/OsSignal and Clock ShieldingCommunicationProblem Solving

What the employer is looking for

  • An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.
  • Bachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp

Preferred qualifications

  • Must have detailed knowledge of CMOS circuit theory.
  • Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
  • Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
  • Must have at least 8 years of relevant or comparable experience doing analog layout design
  • Knowledge of chip level integration and ESD concepts a plus
  • Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
  • Good understanding of signal and clock shielding and isolation techniques
  • Ability to work well as part of a team

Benefits and support

  • Compensation and benefits are detailed in the job posting

About AMD

AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.

Industry
Semiconductors
Company size
31000 employees
Founded
1969-05-01
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company

  • 2007-11-16Post Ipo

Leadership

DL
Dr. Lisa Su

Chair and Chief Executive Officer

JH
Jean Hu

Executive Vice President, Chief Financial Officer and Treasurer

MP
Mark Papermaster

Executive Vice President and Chief Technology Officer

PG
Philip Guido

Executive Vice President and Chief Commercial Officer

FN
Forrest Norrod

Executive Vice President and General Manager, Data Center Solutions Business Group

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