RTL Design Specialist - UFS/MMC/USB/PCIe/UCIe/I2C/I3C/SMBus/SPI/UART Subystems
Samsung Semiconductor · Posted Oct 8
Advanced memory, foundry, system LSI, and semiconductor manufacturing solutions
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About the role
Samsung Semiconductor India Research (SSIR), one of Samsung Electronics' largest R&D centers outside Korea, works on industry-leading semiconductor solutions spanning System LSI, Memory, Foundry, mobile SoCs, storage solutions, AI/ML, 5G/6G, neural processors and serial interfaces. The team focuses on SoC subsystem architecture, high-level integration, bus fabric and connectivity protocols including PCIe/UCIe, NoC and high-bandwidth interconnects, as well as storage and peripheral fabric such as UFS/MMC/USB. This role leads architectural definition and subsystem-level integration, covering micro-architecture and hardware design documents, AMBA protocol compliance, timing closure, low-power and validation flows.
What you will do
- Job Summary: Lead the architectural definition and subsystem-level integration
- Architectural Definition: Define the subsystem structure and NoC concepts for PCIe Gen 5/6/7 and UCIe ,. Create micro-architecture and Hardware Design Documents (HDD).
- Protocol Mastery: Ensure strict compliance with AMBA CHI, ACE, and AXI protocols for high-performance data movement.
- System Integration: Manage the integration of interconnect IPs into the SoC top-level, focusing on latency tuning and bandwidth optimization.
- Quality & Timing: Drive SDC constraints, STA Timing analysis, and Formality checks at the subsystem level.
- Validation & Collab: Lead pre- and post-silicon validation and work collaboratively with global SoC teams across various geographies.
- Flows: Oversee RTL Lint, CDC, UPF/VCLP low-power checks, and DFT checks. Use Verdi for system-level debugging.
Skills used in this role
What the employer is looking for
- 5 –18 years of experience in SoC/IP RTL Design and Subsystem Architecture.
- Strong expertise in storage or high-speed peripheral protocols, including UFS, MMC, and USB (2.0/3.0/SS), PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc
- Sound knowledge of the complete AMBA protocol stack, specifically AXI, AHB, and APB.
- Expert-level experience in low-power architecture design using UPF and VCLP.
- Proven track record in managing GLS (Gate Level Simulation) closure and implementing Functional ECOs.
- Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 and UCIe specifications.
- Sound knowledge of the complete AMBA protocol stack, with mastery of CHI, ACE, and AXI.
- Proven experience in NoC (Network-on-Chip) concepts, interconnect topology, and performance/latency tuning.
- Deep understanding of SDC constraints, STA Timing analysis, and high-frequency timing closure.
- Strong grasp of RTL Lint, CDC, SDC constraints, and DFT checks for complex subsystems.
- Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 , UCIe , UFS, MMC,USB ,PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc specifications.
- Experience in driving system-level RTL Lint, CDC, Formality, and Low-power checks (UPF, VCLP).
Benefits and support
- Compensation and benefits are detailed in the job posting
About Samsung Semiconductor
Samsung Semiconductor is a world leader in advanced memory technology, integrated circuits, and semiconductor foundry services. Part of Samsung Electronics, the company develops essential hardware components like DRAM, NAND flash, application processors, and sensor solutions that power global computing, mobile, and AI infrastructure. Through continuous innovation in lithography and packaging, Samsung drives technological advancements across consumer electronics and enterprise data centers.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1969
- Location
- San Jose, California, USA
- Funding stage
- Public Company
Leadership
Jinman Han
President of Foundry Business
Yong-In Park
President of System LSI Business
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