Principal Engineer, SRAM Design
Micron · Posted Nov 3
DRAM, NAND, HBM memory and computer data storage solutions
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About the role
Micron Technology is a leader in memory and storage solutions, delivering DRAM, NAND and NOR products across data center, edge, client and mobile applications. This role sits in the custom memory IP design area, developing high-performance SRAM and register-file memory IP and testchip content for advanced semiconductor technologies. The Principal SRAM Design Engineer works on architecture definition, transistor-level circuit design, simulation and verification, and partners with layout, CAD, process integration and testchip teams to deliver production-ready memory solutions.
What you will do
- Design, Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, etc.
- Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
- Own transistor-level simulation and signoff using Spectre/FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation, and waveform/debug reviews.
- Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction, and layout-dependent effects.
- Develop or improve automation for simulation setup, corner execution, results extraction, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.
- Plan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans, and alignment with process-learning goals.
- Engage process and foundry partners to understand device behavior, variation, layout restrictions, reliability constraints, and technology-specific opportunities affecting SRAM design margins.
- Create clear circuit specifications, design-review material, verification plans and release documentation with traceable assumptions and decisions.
- Mentor engineers on memory-circuit fundamentals, simulation discipline, PPA analysis, debug methods, and reusable design practices.
- Explore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis, and documentation while maintaining human technical review.
Skills used in this role
What the employer is looking for
- SRAM and register-file architectures, bitcell arrays, local and global datapaths, sensing, write paths, decoding, control, clocking, test access, and retention behavior.
- Low-power and high-performance design techniques including assist circuits, biasing, leakage reduction, dynamic-power optimization, robust low-voltage operation, and variation-aware sizing.
- Memory compilers and configurable macro generation, including architecture templating, legal configuration space, multi-view collateral, validation, and customer or SoC integration support.
- Circuit verification using spice simulators, PVT analysis, Monte Carlo mismatch, extracted post-layout simulation, and timing/power model correlation.
- Testchip development, silicon data analysis, debug, model calibration analysis, and process integration collaboration.
- Demonstrated industry experience of 8+ yars in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.
- BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.
- Strong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.
- Hands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.
- Experience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.
- Ability to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.
- Experience collaborating with layout, CAD, process/foundry, verification, product, and silicon characterization teams.
- Clear technical communication, structured problem solving, and the ability to debug complex circuit or silicon issues using data and waveform evidence.
Preferred qualifications
- Experience developing low-power SRAM compilers or register-file compilers across multiple technology nodes and foundries.
- Experience with bitcell and peripheral circuit stability analysis, PPA aware design schemes, and memory validation.
- Track record of taking memory IP from product definition and circuit design through layout, simulations, release, and silicon correlation.
- Experience planning memory testchips and partnering with silicon test teams on characterization, debug, and correlation.
- Proficiency in Python, Tcl, Perl, SKILL, or similar languages for simulation, characterization, regression, and design-flow automation.
- Familiarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.
- Experience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Micron
Micron Technology, Inc. is a world leader in innovative memory and storage solutions, manufacturing DRAM, NAND, NOR, and High Bandwidth Memory (HBM) technologies. The company provides foundational computing capabilities for artificial intelligence, 5G, data centers, and consumer electronics worldwide. Headquartered in Boise, Idaho, Micron plays a critical role in powering next-generation computing architectures.
- Industry
- Semiconductors
- Company size
- 56,000 employees
- Founded
- October 5, 1978
- Location
- Boise, Idaho, USA
- Funding stage
- Public Company
Leadership
Chairman and Chief Executive Officer
Executive Vice President and Chief Financial Officer
President and Chief Operating Officer
President and Chief Technology and Products Officer
Executive Vice President and Chief People Officer
Senior Vice President, Chief Legal Officer and Corporate Secretary
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