PMTS - DFT Architect
AMD · Posted Oct 18
High-performance processors, graphics cards, data center solutions, and AI accelerators
Get a personal compatibility score
Add a resume for personal matches
About the role
AMD's Circuit Technologies (CT) team works on DFT design and integration for next-generation SoCs and chiplets, spanning SCAN, ATPG, MBIST, BSCAN and broader DFX architectures for debug, test, validation, reliability and manufacturability. The role partners with SoC/chiplet and IP architects to define future DFx architectures and contribute to product and micro-architecture specifications, performance and power trade-offs. As a PMTS Silicon Design Engineer, this position leads DFT design and integration from early concept development through to final production.
What you will do
- Develop next-generation SoC/chiplet and IP debug and observability solutions that enable secure, scalable, and robust silicon bring-up, validation, and post-silicon debug.
- Partner with architecture and SoC/chiplet and IP design teams to define and execute a comprehensive Design-for-Excellence (DFX) strategy spanning debug, test, validation, reliability, and manufacturability.
- Collaborate with technology, silicon validation, product engineering, and manufacturing teams to establish DFX architectures that support both functional operating modes and manufacturing test requirements.
- Drive cross-functional alignment on DFX requirements, use cases, and end-to-end implementation flows across AMD engineering organizations.
- Evaluate and deploy AI-driven methodologies to streamline DFX planning, insertion, verification, coverage analysis, and implementation, improving quality, consistency, and scalability while reducing manual effort and time-to-deployment.
- Define metrics, methodologies, and automation frameworks to ensure DFX solutions meet product quality, testability, debug, and production readiness objectives across multiple programs and technology generations.
Skills used in this role
What the employer is looking for
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Preferred qualifications
- 10+ years of experience in SoC/chiplet and IP design, DFX architecture, or related silicon development disciplines.
- Strong understanding of DFX implementation and integration within complex, large-scale SoC/chiplet architectures.
- Deep knowledge of DFT methodologies and infrastructure, including scan, ATPG, MBIST, JTAG 1149.x/boundary scan, and advanced debug and test features.
- Solid understanding of SoC clocking, reset, power management, and low-power design architectures.
- Strong analytical, organizational, and communication skills with the ability to collaborate effectively across diverse engineering teams and disciplines.
- Demonstrated ability to decompose complex technical problems, evaluate tradeoffs, and develop solutions from both architectural and implementation perspectives.
- Experience applying AI and data-driven techniques to improve engineering productivity, including DFX requirement analysis, insertion planning, verification, coverage assessment, validation, and design quality optimization.
- Ability to leverage modern AI-assisted engineering workflows and tools to accelerate debug, reduce manual effort, improve consistency, and enable earlier identification of design and DFX risks.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
Recent coverage
AMD Newsroom
OCP 2026: AMD CEO Lisa Su Highlights Open Infrastructure for the Future of AI2026-10-12
AMD Newsroom
Introducing AMD Helion, Agentic AI Compute at Rack Scale2026-10-12
TweakTown
AMD CEO Lisa Su calls 2026 the 'year of inference' and says the CPU market will grow tenfold to $200B by 20302026-10-14