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Physical Design Sr / Lead / Staff Engineer - Camera

Qualcomm · Posted Sep 25

Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions

Bangalore, IndiaFull-timeOnsiteLead/Staff3–15 years₹40.0L–₹80.0L yearly100+ applicants
SemiconductorsWireless TechnologyTelecommunicationsArtificial IntelligenceMobile ComputingPublic Company
Full time

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About the role

The role sits within Qualcomm's Hardware Engineering Group, focused on Physical Design for Camera PNR implementation. The engineer will drive end-to-end physical design from netlist to GDSII, collaborating with Design and CAD teams to solve critical physical design challenges and hit stringent PPA targets. It is a senior/lead-level onsite position based in Bangalore, India.

What you will do

  • Collaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.
  • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.
  • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.
  • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.

Skills used in this role

Physical DesignFloorplanningPlace and RoutePnRClock Tree SynthesisCTSSTASignoffGDSIINetlistPVLECLow Power DesignPDNPPAFusion CompilerGenusInnovusPrimeTimeTempusVoltusRedHawkIR Drop AnalysisPhysical VerificationECOTiming ConvergenceTweakerVoltage IslandsVLSIPower OptimizationPerlPythonTclCamera

What the employer is looking for

  • 3 - 15 years of experience in Physical Design, including floorplanning, Place & Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks
  • Hands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure
  • Experience with voltage islands and low-power design methodologies, flows, and implementation
  • Strong focus on achieving optimal PPA (Power, Performance, Area)
  • Strong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, PrimeTime (PT), Tempus, Voltus, and RedHawk
  • Solid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification
  • Experience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime
  • Knowledge of power optimization techniques and methods to minimize power consumption
  • Strong fundamentals in Physical Design and VLSI concepts
  • Proficiency in scripting languages such as Perl, Python and TCL
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Preferred qualifications

  • Experience in deep submicron technology nodes (preferred)
  • Understanding of high-performance and low-power implementation techniques (preferred)

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Qualcomm

Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.

Industry
Semiconductors
Company size
50000+ employees
Founded
1985
Location
San Diego, California, USA
Funding stage
Public Company

Funding

Public Company · $53M raised

Western Technology Investment
  • 2018-11-01Grant

Leadership

CR
Cristiano R. Amon

President and Chief Executive Officer

AP
Akash Palkhiwala

Chief Financial Officer and Chief Operating Officer

JH

James H. Thompson

Chief Technology Officer

DM
Don McGuire

Chief Marketing Officer

AC

Ann Chaplin

General Counsel and Corporate Secretary