Physical Design Lead with STA
AMD · Posted Oct 7
High-performance processors, graphics cards, data center solutions, and AI accelerators
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About the role
AMD designs processors, AI accelerators and computing technologies, and this role sits within the Physical Design (PD PnR) team. The team owns SoC subsystem physical design closure for high-frequency CPU, HBM, DDR and Serdes interfaces. The role leads RTL-to-GDS execution and closure of 10 or more partitions, driving STA, EMIR and PV signoff while collaborating with methodology and CAD teams across geographies for first-pass silicon success.
What you will do
- Specialized in Clock build , clock push down from top to block, guide tile for latency and skew
- As a member of the PD pnr team responsible for owning and leading SubSystem of 10 or more partitions. SoC SS PD closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for RTL to GDS execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.
- Owns SS Partitions PnR execution and closure
- Drive new improvement in closure
- Analysis of data and feedback to Design team
- Work with PnR team members for closure convergence starting from Synthesis to Route
- Closure signoff on STA, EMIR, PV
- Work and collaborate with different business units, CAD and central methodology team to drive the requirement
- Automation to refine and improve design signoff requirement and dashboarding
- Ability to organize and present complex technical information in a crisp and concise manner.
- Interact with other PPA (equivalent) teams internal to AMD
- Identify best practices across AMD and industry to update and improve flow/project settings
- To increase the competitiveness of each stage in AMD design flow
- Ability to work with multi-level functional teams across various geographies.
- Highly organized, strong affinity for automation and prioritization.
Skills used in this role
What the employer is looking for
- A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
- Strong self-driving ability, should have excellent communication skills (both written and oral)
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Preferred qualifications
- 8+ year or more experience design signoff closure
- Strong PnR backround with critical problem solving ability on improving PPA and debug
- Technical depth in CTS, Route, STA.
- EMIR driven power grid knowledge
- PnR and STA signoff correlation drive and convergence
- Strong at SDC coding and debug skills
- Drive new requirements and methodology to aid timing closure at SoC
- Identify the gaps and support flows
- Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
- Drive team towards common requirements and flows
- Experienced in deploying and implementing ML techniques and algorithms in physical design.
- Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
- Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
- AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
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