Physical Design Engineer- Static Timing Analysis (STA)
IBM · Posted Oct 14
Hybrid cloud, artificial intelligence, enterprise software, quantum computing, and IT consulting services
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About the role
IBM Infrastructure & Technology designs and operates systems such as high-resiliency mainframes, hybrid cloud platforms, networking, automation, and site reliability, ensuring performance, security, and scalability for clients and industries. This role is a Physical Design Engineer with deep expertise in static timing analysis using Cadence Tempus, owning timing closure across multiple blocks and top-level designs. The engineer will work closely with synthesis, PD, and signoff teams to achieve high-performance, low-power SoC designs.
What you will do
- Lead timing closure strategy for full-chip / hierarchical SoC designs using ILM/ETM-based flows
- Own signoff correlation between Tempus and other tools (PrimeTime, Innovus, etc.)
- Drive timing closure across all PVT corners and MMMC modes; debug and resolve timing violations
- Define and enforce timing methodology guidelines across the team; mentor junior/mid-level engineers
- Develop and validate SDC constraints; perform timing ECOs (buffering, resizing, logic restructuring)
- Drive automation – develop reusable TCL/Python scripts for timing analysis, reporting, and waiver management
- Analyze SI, crosstalk, and noise issues; handle Tempus SI for crosstalk delta-delay and glitch analysis
- Interface with Cadence EDA vendor for tool issues and new feature adoption
- Participate in architecture and floorplan reviews to identify timing risks early
- Contribute to DFM and low-power (CPF/UPF) timing signoff; generate timing reports and signoff closure
Skills used in this role
What the employer is looking for
- Cadence Tempus (hands-on)
- Strong STA fundamentals
- MMMC / OCV / AOCV / POCV
- SDC expertise
- Timing ECO methodology
- ILM / ETM / QRC models
- SPEF correlation & back-annotation
- Tempus SI (crosstalk / glitch)
- CTS timing implications
- Multi-Vt / voltage island timing
- Innovus–Tempus in-design timing
- Cadence Conformal ECO
- Unix / Linux & TCL / Python scripting
- Advanced nodes (12nm or below)
- Physical-aware Tempus experience
Preferred qualifications
- Experience with Cadence Innovus or other PD tools
- Understanding of IR/EM and power analysis impacts on timing
- Familiarity with low-power design techniques (UPF/CPF)
- Exposure to signoff methodologies and tapeout cycles
- Knowledge of automation and timing flow optimization
Benefits and support
- Compensation and benefits are detailed in the job posting
About IBM
International Business Machines Corporation (IBM) is a global technology and consulting company that provides hybrid cloud, artificial intelligence, and enterprise infrastructure solutions. Operating in over 175 countries, IBM helps businesses across industries modernize operations, secure data, and drive digital transformation through platforms like watsonx and Red Hat OpenShift. Founded over a century ago, the company remains a pioneer in high-performance computing, enterprise automation, and quantum technology.
- Industry
- Information Technology
- Company size
- 260,000+ employees
- Founded
- June 16, 1911
- Location
- Armonk, New York, USA
- Funding stage
- Public Company
Funding
Public Company · $3.5B raised
- ·Post Ipo Debt$150M
Leadership
Chairman, President and Chief Executive Officer
Senior Vice President and Chief Financial Officer
Senior Vice President, Software and Chief Commercial Officer
Senior Vice President, IBM Consulting
Senior Vice President, Marketing and Communications
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