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Physical Design Engineer, Lead Engineer Senior

Qualcomm · Posted Sep 30

Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions

Hyderabad, Telangana, IndiaFull-timeOnsiteLead/Staff8+ years₹35.0L–₹60.0L yearly100+ applicants
SemiconductorsWireless TechnologyTelecommunicationsArtificial IntelligenceMobile ComputingPublic Company
Full time

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About the role

Qualcomm India Private Limited's Hardware Engineering Group works on ASIC design and implementation. The team owns the physical design flow from netlist to GDS2, covering place and route, low-power methodologies, power integrity, and timing/sign-off closure. This role drives complete PD ownership including floorplanning, PNR, CTS and sign-off checks, and contributes to improving existing methodologies and flows while working in a global team environment.

What you will do

  • Understand and implement improving existing methodologies and flows.
  • To be effectively communicate the status and issues of respective owned Tasks

Skills used in this role

ASICPhysical DesignPlace and RouteFloorplanningClock Tree Synthesis (CTS)Static Timing Analysis (STA)Low Power DesignVoltage IslandsPower Distribution Network (PDN)LECFormal VerificationGDS2NetlistInnovusFusion CompilerTCLPerlPythonSign-offScan-DRCcommunication

What the employer is looking for

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • Thorough knowledge of the ASIC designs Place and Route flow and methodology.
  • Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
  • Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
  • Strong background in debugging Congestion and CTS issues.
  • Expertise in PnR tools (Innovus/Fusion compiler) and flow.
  • Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
  • Proficient in scripting languages (TCL,PERL,PYTHON).
  • Self-starter and highly motivated
  • To have working experience in global team environment.
  • 8+ yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Qualcomm

Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.

Industry
Semiconductors
Company size
50000+ employees
Founded
1985
Location
San Diego, California, USA
Funding stage
Public Company

Funding

Public Company · $53M raised

Western Technology Investment
  • 2018-11-01Grant

Leadership

CR
Cristiano R. Amon

President and Chief Executive Officer

AP
Akash Palkhiwala

Chief Financial Officer and Chief Operating Officer

JH

James H. Thompson

Chief Technology Officer

DM
Don McGuire

Chief Marketing Officer

AC

Ann Chaplin

General Counsel and Corporate Secretary