PD Timing lead
AMD · Posted Oct 23
High-performance processors, graphics cards, data center solutions, and AI accelerators
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About the role
AMD's full-chip timing (FCT) group develops, validates, and maintains timing constraints and drives full-chip timing convergence for complex SoCs. The team owns SDC methodology, timing signoff quality, and cross-domain timing closure in collaboration with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams. This MTS Silicon Design Engineer role focuses on timing analysis and closure across corners, modes, and milestones, plus timing automation, QoR dashboards, methodology improvements, and mentoring junior engineers.
What you will do
- Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC).
- Perform comprehensive timing analysis and closure for full-chip and partition-level designs.
- Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.
- Drive timing convergence across multiple corners, modes, and milestone releases.
- Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.
- Own timing signoff readiness and ensure timing quality across all project deliverables.
- Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks.
- Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.
- Support customer timing reviews, signoff audits, and tapeout readiness activities.
- Mentor junior engineers and provide technical guidance on timing methodologies and best practices.
Skills used in this role
What the employer is looking for
- Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field.
- 7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design.
- Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV.
- Hands-on experience developing and validating SDC constraints.
- Proficiency with Synopsys PrimeTime and timing signoff methodologies.
- Strong understanding of clocking architectures, timing exceptions, and CDC interactions.
- Experience debugging timing violations and driving closure across multiple corners and modes.
- Proficiency in Tcl, Python, Perl, or Shell scripting.
- Strong analytical, problem-solving, and communication skills.
Preferred qualifications
- Experience driving full-chip timing closure for large CPU, GPU, AI/ML, networking, or datacenter SoCs.
- Expertise in constraint quality checks, timing signoff reviews, and correlation methodologies.
- Knowledge of clock-domain crossings, asynchronous interfaces, and timing exception verification.
- Experience with PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, or equivalent EDA tools.
- Familiarity with low-power timing methodologies, UPF flows, and advanced-node signoff requirements.
- Experience supporting tapeouts at 5nm, 4nm, 3nm, or newer process technologies.
- Proven track record of independently driving timing convergence for critical project milestones.
- Experience developing automation, AI-assisted timing analysis flows, and productivity-enhancing methodologies.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
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