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PD Power Lead

AMD · Posted Oct 23

High-performance processors, graphics cards, data center solutions, and AI accelerators

Bangalore, IndiaFull-timeOnsiteSenior Level7–10 years₹35.0L–₹55.0L yearly<25 applicants
SemiconductorsHardwareArtificial IntelligenceCloud ComputingGamingPublic Company
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About the role

AMD designs processors and technologies spanning AI, datacenter, and client computing. This role sits in silicon design, responsible for power analysis, power optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) and related power methodologies. The engineer will drive dynamic and leakage power convergence, identify power bottlenecks, and collaborate across PD, RTL, Architecture, Timing, DFT, and Power teams to achieve product power targets.

What you will do

  • Perform block, tile, and full-chip power analysis using PrimeTime PX (PTPX).
  • Analyze dynamic, leakage, clock, memory, and switching power components to identify optimization opportunities.
  • Drive power convergence across project milestones and signoff stages.
  • Correlate power across RTL, synthesis, implementation, and silicon projections.
  • Debug high-power hotspots and recommend architecture, RTL, clocking, and physical design optimizations.
  • Execute power regression flows and generate power dashboards, reports, and trend analysis.
  • Collaborate with PD, timing, clocking, and RTL teams to implement power-reduction solutions.
  • Develop automation, scripts, and methodologies to improve power analysis efficiency and accuracy.
  • Support power signoff reviews and customer-facing power deliverables.

Skills used in this role

PrimeTime PX (PTPX)PrimeTimeFusion CompilerRedHawkJoulesPowerArtistTclPythonPerlShell ScriptingASICSTAPhysical DesignSynthesisRTLDFTClockingCMOSLow-Power DesignDVFSSAIFVCDUPFCPFSoC

What the employer is looking for

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Computer Engineering, or related field.
  • 7 to 10 years of experience in ASIC Physical Design, STA, or Power Analysis.
  • Strong understanding of digital design, CMOS power fundamentals, and low-power design techniques.
  • Hands-on experience with PrimeTime PX (PTPX) or equivalent power analysis tools.
  • Good understanding of activity propagation, SAIF/VCD-based power analysis, and switching activity estimation.
  • Familiarity with synthesis, STA, clocking, and physical design flows.
  • Proficiency in Tcl, Python, Perl, or Shell scripting.
  • Strong analytical, debugging, and problem-solving skills.

Preferred qualifications

  • Experience in SoC power signoff for CPU, GPU, AI/ML, networking, or datacenter products.
  • Strong understanding of clock power optimization, power gating, multi-Vt strategies, DVFS, and low-power methodologies.
  • Experience correlating RTL power, implementation power, and silicon power measurements.
  • Exposure to advanced process nodes (5nm, 4nm, 3nm, or below).
  • Experience with PrimeTime, Fusion Compiler, RedHawk, Joules, PowerArtist, or similar EDA tools.
  • Knowledge of UPF/CPF, IR/EM considerations, and thermal-aware power analysis.
  • Ability to independently drive power closure for critical blocks and mentor junior engineers.
  • Experience developing power automation flows, dashboards, and AI-assisted power optimization methodologies.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About AMD

AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.

Industry
Semiconductors
Company size
31000 employees
Founded
1969-05-01
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company

  • 2007-11-16Post Ipo

Leadership

DL
Dr. Lisa Su

Chair and Chief Executive Officer

JH
Jean Hu

Executive Vice President, Chief Financial Officer and Treasurer

MP
Mark Papermaster

Executive Vice President and Chief Technology Officer

PG
Philip Guido

Executive Vice President and Chief Commercial Officer

FN
Forrest Norrod

Executive Vice President and General Manager, Data Center Solutions Business Group

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