PD PNR Engineer
AMD · Posted Oct 2
High-performance processors, graphics cards, data center solutions, and AI accelerators
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About the role
AMD designs next-generation processors and silicon technology, spanning AI, scientific discovery, and everyday computing platforms. This role sits within silicon design, focused on end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating with RTL, architecture, CAD, timing, clocking, and full-chip teams.
What you will do
- Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff.
- Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization.
- Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets.
- Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration.
- Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges.
- Support milestone deliveries and ensure quality execution aligned with project schedules.
- Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency.
- Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing.
Skills used in this role
What the employer is looking for
- Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, Computer Engineering, or related field.
- 7 to 10 years of experience in Physical Design or ASIC implementation.
- Strong understanding of digital design fundamentals and VLSI implementation flows.
- Hands-on experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation.
- Good understanding of STA concepts, timing optimization, and physical design signoff requirements.
- Proficiency in scripting using Tcl, Python, Perl, or Shell.
- Strong debugging, analytical, and problem-solving skills.
- Excellent communication and cross-functional collaboration abilities.
Preferred qualifications
- Experience in converging large and complex CPU, GPU, NOC, AI/ML, or networking tiles.
- Exposure to advanced technology nodes (5nm, 4nm, 3nm or below).
- Knowledge of power optimization, EMIR, CDC, RDC, and physical verification methodologies.
- Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, RedHawk, or equivalent EDA tools.
- Proven track record of independently leading critical tiles and driving milestone deliveries.
- Experience in PPA optimization, methodology development, AI-assisted PD flows, and automation initiatives.
- Ability to guide junior engineers and act as a technical lead for assigned tiles.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
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