PD Lead
AMD · Posted Oct 9
High-performance processors, graphics cards, data center solutions, and AI accelerators
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About the role
AMD designs next-generation processors and advanced technologies spanning healthcare, scientific discovery, and AI. This PMTS Silicon Design Engineer / PHY-V Lead role owns physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs, driving DRC/LVS clean tapeouts and sign-off predictability across complex multi-IP designs. The position leads cross-functional execution with PD, Analog, and Packaging teams and mentors PHY-V engineers.
What you will do
- Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
- Define and enforce sign-off methodology and quality criteria
- Own foundry rule decks, waivers, and risk assessments
- Deliver sign-off clean GDS for tapeout
- Lead top-level integration of IPs/macros into SoC
- Own: GDS assembly
- Own: Hierarchical LVS reconciliation
- Resolve: Boundary issues
- Resolve: Connectivity mismatches
- Resolve: Integration conflicts
- Ensure robust integration across internal and third-party IPs
- Drive RDL planning and bump mapping strategy
- Define IO escape routing and die–package interface
- Collaborate with Packaging, SI/PI, and system teams
- Enable flip-chip / 2.5D / 3D integration readiness
- Own sign-off checklist, closure tracking, and tapeout readiness
- Lead tapeout reviews and milestone tracking
- Drive cross-team closure to meet schedule and quality targets
- Define and improve physical verification flows (Calibre/ICV/Pegasus)
- Drive: Automation (TCL/Python)
- Drive: Runtime optimization
- Drive: Debug efficiency
- Establish best practices for hierarchical and incremental sign-off
- Lead debug of: Complex DRC violations
- Lead debug of: LVS mismatches (shorts/opens/connectivity issues)
- Drive closure with PD/layout teams
- Minimize waivers and ensure risk-managed sign-off
- Lead and mentor PHY‑V engineers
- Act as primary escalation point for sign-off issues
- Interface with: PD / PnR teams
- Interface with: Analog/layout teams
- Interface with: Packaging and foundry teams
Skills used in this role
What the employer is looking for
- Strong technical leader with deep PD + Physical Verification understanding
- Proven ownership of sign-off closure for complex SoCs
- Ability to drive execution across multiple teams and dependencies
- Detail-oriented with focus on quality, manufacturability, and schedule predictability
- Comfortable operating in high-pressure tapeout environments
- B.Tech / M.Tech in Electronics / Electrical Engineering
- 10–15+ years in Physical Design / Physical Verification / SoC Integration
- Strong expertise in: DRC, LVS, ERC, antenna checks
- Tools: Calibre / ICV / Pegasus
- Solid understanding of: Full PD flow (RTL → GDS → sign-off)
- Solid understanding of: Advanced process nodes (7nm and below)
Preferred qualifications
- Experience in: Full-chip SoC integration and GDS assembly
- Experience in: RDL planning and advanced packaging flows
- Exposure to: IR/EM, SI/PI, PEX, reliability checks
- Exposure to: Chiplet / 2.5D / 3D-IC methodologies
- Strong scripting (TCL/Python) for automation
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
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