PD Engineer
AMD · Posted Oct 15
High-performance processors, graphics cards, data center solutions, and AI accelerators
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About the role
AMD develops advanced processors, AI-enabling technologies, and leading-edge products, and this role sits within its chip design organization. The IR/EM Lead drives reliability signoff and closure for advanced SoC and IP designs, ensuring robust power delivery and electromigration compliance from floorplan through tapeout. The role covers static and dynamic IR-drop analysis, electromigration verification, power grid and decap planning, methodology and automation development, and cross-functional technical leadership and mentoring.
What you will do
- Lead all IR/EM activities for complex SoC and IP programs from floorplan through tapeout.
- Define and drive project-wide IR/EM closure strategies, schedules, and signoff criteria.
- Perform and review static and dynamic IR-drop analysis across full-chip and block-level designs.
- Lead electromigration analysis and closure for power grids, clock networks, signal routing, and package interfaces.
- Collaborate closely with Physical Design, Package Design, Power Architecture, Clock, RTL, CAD, and Technology teams.
- Identify power integrity risks early and drive mitigation plans through implementation and signoff stages.
- Develop and deploy methodologies, automation, dashboards, and best practices to improve IR/EM convergence.
- Guide teams in power grid architecture, decap planning, bump assignment, power distribution optimization, and reliability improvements.
- Drive technical reviews and communicate design health, risks, and recommendations to project leadership.
- Mentor engineers and provide technical leadership across multiple projects.
- Act as the primary technical owner for IR/EM signoff and closure.
- Drive technical decisions impacting product reliability and design quality.
- Influence implementation methodology across project and organizational boundaries.
- Lead root-cause analysis for power integrity issues and drive systematic improvements.
- Coach engineers and establish technical best practices for reliability signoff.
Skills used in this role
What the employer is looking for
- Strong expertise in Power Integrity and Electromigration analysis methodologies.
- Deep understanding of:
- Static and Dynamic IR Analysis
- Electromigration Verification
- Power Grid Design and Optimization
- Decap Planning and Analysis
- Voltage Drop Debug and Closure
- Advanced Node Reliability Requirements
- Hands-on experience with industry-standard IR/EM signoff tools.
- Strong scripting and automation skills (Python, Tcl, Perl, or similar).
- Strong understanding of advanced-node physical design implementation flows.
- BS/MS in Electrical Engineering, Computer Engineering, or related discipline.
- Typically 5-15 years of experience in Physical Design, Power Integrity, Reliability Analysis, or Signoff Engineering.
- Proven experience leading IR/EM closure for large SoC designs through successful tapeout.
Preferred qualifications
- Experience with 5nm, 4nm, 3nm, or newer process technologies.
- Understanding of package and system-level power delivery networks.
- Familiarity with thermal analysis and reliability methodologies.
- Experience developing automation and signoff productivity frameworks.
- Strong communication and project leadership skills.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
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