NOC Design Engineer
L&T Semiconductor Technologies · Posted Oct 12
Advanced fabless semiconductor chip design and power electronics solutions for automotive, industrial, and energy markets
Get a personal compatibility score
Add a resume for personal matches
About the role
L&T Semiconductor Technologies (LTSCT) is building the xPU compute architecture, in which a stacked Network-on-Chip forms the data backbone — four physical planes delivering 12 TB/s cross-section bandwidth. This role owns coherency, routing, QoS, and bandwidth allocation across the BFOS arrays, banked SRAM, HBM controllers, UCIe links, and the host interface. The NoC Design Lead will architect and implement the NoC, drive micro-architecture and RTL integration, and close latency, bandwidth and congestion targets in collaboration with physical design and verification teams.
What you will do
- Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross-section bandwidth across all on-chip and off-chip endpoints.
- Define topology, routing algorithms, virtual channels, and arbitration to guarantee deadlock-free, high-throughput data movement.
- Design QoS and bandwidth-allocation mechanisms balancing traffic between dual BFOS arrays, 512 SRAM banks, HBM controllers, UCIe, and host.
- Own the on-chip coherency protocol and its interaction with SRAM, HBM, and the host-interface coherency layer.
- Drive micro-architecture, RTL, and integration of routers, network interfaces, buffers, and clock-domain crossings.
- Model and analyze latency, bandwidth, and congestion via cycle-accurate simulation and traffic generators; close performance targets.
- Collaborate with PD on floorplan-aware NoC partitioning across the 4 physical planes and with DFT/verification on coverage.
- Define QoR/performance metrics, mentor engineers, and represent NoC in architecture and integration reviews.
Skills used in this role
What the employer is looking for
- 10+ years designing on-chip interconnects/NoCs or coherent fabrics for high-performance SoCs.
- Deep understanding of NoC topologies (mesh, torus, crossbar, stacked/multi-plane), routing, flow control, and QoS.
- Strong grasp of cache-coherency protocols (MESI/MOESI-class, directory-based) and memory-consistency models.
- Expertise in RTL design (SystemVerilog) of routers, arbiters, buffers, and asynchronous/CDC interfaces.
- Hands-on performance modeling and analysis — cycle-accurate simulation, traffic modeling, bandwidth/latency closure.
- Experience with commercial or in-house NoC generators/IP and their integration methodology.
- Familiarity with high-bandwidth memory (HBM) and chiplet interconnect (UCIe) traffic characteristics.
- Proficiency in scripting (Python/Perl) for performance analysis and verification support.
- Strong micro-architecture, specification, and documentation skills.
- Demonstrated technical leadership and cross-team collaboration.
Preferred qualifications
- Experience with multi-plane or 3D-stacked NoC architectures.
- Background in AI accelerator or GPU dataflow interconnects.
- Familiarity with formal verification of coherency/deadlock properties.
- M.Tech/MS in EE/ECE/CS or equivalent.
Benefits and support
- Compensation and benefits are detailed in the job posting
About L&T Semiconductor Technologies
L&T Semiconductor Technologies (LTSCT) is a fabless semiconductor company specializing in advanced chip design, SiC and GaN power semiconductors, and sustainable technology solutions. Backed by the engineering legacy of Larsen & Toubro, the company develops high-performance power, sense, and compute semiconductor solutions tailored for automotive, industrial, and energy sectors globally.
- Industry
- Semiconductors
- Company size
- 251-500 employees
- Founded
- 2023
- Location
- Mumbai, Maharashtra, India
- Funding stage
- Corporate Subsidiary
Funding
Corporate Subsidiary · ₹859 Cr raised
Leadership
Chief Executive Officer
Rahul Nilosey
Chief Financial Officer
Sekharipuram Narayanan Subrahmanyan
Chairman
Recent coverage
Livemint
L&T Semiconductor Technologies looks to build 3 fabs in India, contingent on generating revenues2024-08-13
Entrepreneur India
The Risk Taker: Sandeep Kumar, CEO, L&T Semiconductor Technologies2024-10-31