MTS - Analog Layout
Micron · Posted Oct 16
DRAM, NAND, HBM memory and computer data storage solutions
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About the role
Micron Technology is a world leader in innovating memory and storage solutions, delivering high-performance DRAM, NAND, and NOR memory and storage products. The Analog Layout team owns full-custom physical implementation of complex Analog and Mixed-Signal IP such as bandgaps, LDOs, charge pumps, PLLs, and ESD structures on advanced FinFET and planar CMOS nodes. This role leads layout from floor-planning through tape-out and signoff, mentors junior engineers, and drives AI-assisted layout and verification methodologies.
What you will do
- Lead full-custom layout for complex Analog / Mixed-Signal IP blocks, including but not limited to:
- Bandgap references, LDOs and regulators, Charge pumps (positive/negative)
- PLLs, delay lines, oscillators, IO & PHY-related analog blocks
- Temperature sensors, bias circuits
- ESD protection devices and clamps
- Own layout quality from floor-planning to tape-out, ensuring:
- Device matching and symmetry, noise isolation and substrate strategies
- Robust power/ground planning
- Yield, reliability, and DFM compliance
- Work closely with circuit designers to translate performance goals into layout strategies, especially in noise-sensitive mixed-signal environments.
- Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
- Review and address issues related to:
- EM/IR, latch-up, ESD window compliance
- Device stress and matching degradation
- Interface with foundry and CAD teams for waiver management and signoff convergence.
- Provide technical guidance and design reviews for junior and mid-level layout engineers.
- Establish and document best-known methods (BKMs) for AMS layout across nodes.
- Drive IP reuse, layout template development, and methodology improvements.
Skills used in this role
What the employer is looking for
- Strong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:
- Fin quantization awareness
- Multi-Vt, multi-fin strategies
- Advanced metal stack planning
- Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.
- Deep understanding of foundry PDKs, layout-dependent effects (LDEs), and process variability.
- Strong understanding of AI/ML and Generative AI concepts, with ability to identify high-value applications in circuit layout.
- Proficiency in Python/scripting and EDA automation to develop AI-assisted layout and verification solutions.
- Ability to translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.
- Experience developing, integrating, and validating AI-driven methodologies against traditional designer-driven flows.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Micron
Micron Technology, Inc. is a world leader in innovative memory and storage solutions, manufacturing DRAM, NAND, NOR, and High Bandwidth Memory (HBM) technologies. The company provides foundational computing capabilities for artificial intelligence, 5G, data centers, and consumer electronics worldwide. Headquartered in Boise, Idaho, Micron plays a critical role in powering next-generation computing architectures.
- Industry
- Semiconductors
- Company size
- 56,000 employees
- Founded
- October 5, 1978
- Location
- Boise, Idaho, USA
- Funding stage
- Public Company
Leadership
Chairman and Chief Executive Officer
Executive Vice President and Chief Financial Officer
President and Chief Operating Officer
President and Chief Technology and Products Officer
Executive Vice President and Chief People Officer
Senior Vice President, Chief Legal Officer and Corporate Secretary
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