Layout Engineer
Arm · Posted Nov 2
Semiconductor IP, energy-efficient CPU architecture, and high-performance compute platforms
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About the role
Arm's Solutions Engineering Physical IP team comprises experts in deep submicron circuit design, building custom standard cell libraries used across infrastructure, client, automotive, and IoT market segments. The team works on the latest sub-3nm process technology nodes, delivering high-performance, area-optimized, DRC-clean logic libraries for next-generation SoCs and custom digital IPs. This Layout Engineer role covers layout development of Arm custom standard cells, DRC/LVS closure, physical view debugging, and automation of layout QA and PDK-driven verification flows in close collaboration with circuit designers, PDK, and QA teams.
What you will do
- Layout design of logic standard cells (inverters, muxes, flops cells, complex logic gates) optimized for performance, area, and power.
- Work with automation and QA teams to support library validation flows.
- Collaborate with circuit designers to understand schematics and translate them into clean, compact layouts.
- Drive design rule clean (DRC) and layout vs. schematic (LVS) closure using industry-standard verification tools (e.g., Calibre ).
- Perform layout debugging and root-cause analysis for DRC, LVS, and other physical sign-off issues.
- Handle cell abutment, cell profiling, and cell integration constraints for logic libraries.
- Address layout-dependent effects (LDE) and double patterning/EUV compliance in advanced nodes.
- Review and debug standard cell physical views (LEF, GDS, abstract views) for integration into digital flows.
- Automate layout QA, regression checks, and PDK-driven layout verifications using scripts (e.g., SKILL, Python).
- Participate in library quality audits and delivery cycles including signoff package creation and documentation.
Skills used in this role
What the employer is looking for
- 1 to 3 years of custom layout experience in logic standard cell development.
- Proven track record of working at 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.
- Proficiency in Cadence Virtuoso.
- Deep understanding of advanced DRC rules, LVS methodologies, and multi-patterning constraints.
- Solid experience in cell layout optimization for PPA (Power, Performance, Area).
- Strong grip on pin accessibility, cell architecture trade-offs, and physical synthesis-aware design.
- Automate layout-related tasks and workflows using scripting languages like Python, PERL, SKILL, and TCL.
- Maintain accurate documentation of layout designs, changes, and verification results.
- Working knowledge of version control, configuration management, and flow automation
- Make effective use of AI tools and automation to improve productivity, accelerate learning, and enhance the quality of technical solutions
- Strong documentation and communication skills to interface with cross-functional teams (PDK, design, QA).
- Stay updated on best practices for standard cell layout, design rules, and advanced node requirements.
Preferred qualifications
- Exposure to physical design implementation flow
Benefits and support
- Hybrid working with team-determined flexible working patterns
About Arm
Arm architects, develops, and licenses high-performance, energy-efficient CPU products and related semiconductor intellectual property. Its technology powers over 99% of the world's smartphones as well as a vast array of devices ranging from tiny sensors and wearables to cloud-scale AI supercomputers.
- Industry
- Semiconductors
- Company size
- 8000+ employees
- Founded
- 1990
- Location
- Cambridge, United Kingdom
- Funding stage
- Public Company
Funding
Public Company
- 2023-09-14IPO$5.23B
Leadership
Chief Executive Officer, Board Member
Executive Vice President and Chief Financial Officer
Executive Vice President, Chief Legal Officer and Head of Corporate Development
Executive Vice President and Chief Commercial Officer
Executive Vice President and Chief Architect
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