Full Chip Timing Lead
AMD · Posted Oct 7
High-performance processors, graphics cards, data center solutions, and AI accelerators
Get a personal compatibility score
Add a resume for personal matches
About the role
AMD's PD Full Chip STA closure and optimization team drives SoC full chip timing closure and optimization across high frequency CPU, HBM, DDR and Serdes interfaces. The role owns full chip timing closure, SDC validation and timing signoff execution, working closely with methodology, CAD and PnR teams across geographies to achieve first pass silicon success. The engineer also drives common STA methodology within the business unit and automation to improve design signoff and dashboarding.
What you will do
- As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. You will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.
- Owns Full chip Timing Closure
- Drive new improvement in closure
- Analysis of data and feedback to PD execution team
- SDC analysis and feedback
- Work with PnR engineer for timing convergence
- Drive the common STA methodology in the business unit
- Work and collaborate with different business units, CAD and central methodology team to drive the requirement
- Automation to refine and improve design signoff requirement and dashboarding
- Ability to organize and present complex technical information in a crisp and concise manner.
- Interact with other PPA (equivalent) teams internal to AMD
- Identify best practices across AMD and industry to update and improve flow/project settings
- To increase the competitiveness of each stage in AMD design flow
- Ability to work with multi-level functional teams across various geographies.
- Highly organized, strong affinity for automation and prioritization.
Skills used in this role
What the employer is looking for
- Bachelors with 7 years of experience or Masters degree with 5 years experience in timing
Preferred qualifications
- Timing closure experience at SoC and block level
- Technical depth in STA, High freq interface closure in hierarchical STA.
- Multi voltage closure
- Timing ECO flow
- Hyperscale, Yield analysis
- PnR and STA signoff correlation drive and convergence
- Strong at SDC coding and debug skills
- Drive new requirements and methodology to aid timing closure at SoC
- Identify the gaps and support flows
- Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
- Drive team towards common requirements and flows
- Experienced in deploying and implementing ML techniques and algorithms in physical design.
- Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
- Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
- AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
Recent coverage
Taipei Times
AMD to 'Substantially' Up Capacity: CEO2026-10-07
AMD Newsroom
AMD to Report Fiscal Third Quarter 2026 Financial Results2026-10-06
Venture Atlas
AMD Agrees to Buy World Labs for About $8.2 Billion2026-09-29