Engineer - Physical design
Arm · Posted Oct 27
Semiconductor IP, energy-efficient CPU architecture, and high-performance compute platforms
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About the role
Arm’s SoC implementation team works on next-generation SoC projects across the synthesis-to-GDSII flow. The role involves physical implementation, timing analysis, debugging, and power, performance, and area (PPA) optimization. The engineer collaborates with design, verification, DFT, and physical IP teams and uses scripting and AI-assisted workflows to improve engineering efficiency.
What you will do
- Complete and support RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation with mentorship from senior engineers.
- Analyze and improve PPA through synthesis and physical implementation.
- Conduct static timing analysis with Synopsys PrimeTime, troubleshoot setup and hold violations, and assist in achieving timing closure across operating modes and corners.
- Review timing constraints, tool reports and implementation results to identify issues, investigate root causes and propose fixes.
- Assist with physical verification and final approval processes, including DRC, LVS, signal integrity, and EM/IR analysis.
- Develop Python and Tcl scripts to automate implementation tasks, analyze reports and track quality.
- Use approved AI tools and agents to assist with scripting, report analysis and debugging, while independently validating their outputs.
- Document results, communicate technical findings and collaborate with teams to resolve implementation issues.
Skills used in this role
What the employer is looking for
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Microelectronics, VLSI or a related field.
- 1–2 years of relevant experience in ASIC/SoC physical design or implementation.
- Familiarity with the RTL-to-GDSII process, encompassing synthesis, floorplanning, placement, CTS, routing, and timing closure.
- Understanding of physical designfundamentals, including utilization, congestion, clock skew, latency, buffering and cell sizing.
- Hands-on experience with PrimeTime and at least one synthesis or physical implementation tools such as Fusion Compiler, Genus or Innovus.
- Knowledge of static timing analysis, including setup/hold checks, clock definitions, timing exceptions and multi-mode, multi-corner analysis.
- Ability to read Verilog RTL and gate-level netlists and trace timing paths to investigate implementation issues.
- Practical programming skills in Python, familiarity with Tcl, and confidence working in a Linux environment.
- Strong analytical and debugging skills, clear communication and a willingness to learn and take ownership of assigned tasks.
Preferred qualifications
- Exposure to advanced-node, hierarchical implementation or large SoC integration.
- Familiarity with low-power concepts, UPF, multiple voltage domains, power gating and level shifters.
- Exposure to on-chip variation, timing derates, crosstalk and signal integrity.
- Basic knowledge of power distribution networks, EM/IR analysis, IO placement, and bump-planning considerations.
- Familiarity with DFT requirements and physical verification flows.
- Experience using AI coding assistants or agents for engineering automation, including effective task definition, output validation and responsible handling of proprietary build data.
Benefits and support
- Hybrid working
About Arm
Arm architects, develops, and licenses high-performance, energy-efficient CPU products and related semiconductor intellectual property. Its technology powers over 99% of the world's smartphones as well as a vast array of devices ranging from tiny sensors and wearables to cloud-scale AI supercomputers.
- Industry
- Semiconductors
- Company size
- 8000+ employees
- Founded
- 1990
- Location
- Cambridge, United Kingdom
- Funding stage
- Public Company
Funding
Public Company
- 2023-09-14IPO$5.23B
Leadership
Chief Executive Officer, Board Member
Executive Vice President and Chief Financial Officer
Executive Vice President, Chief Legal Officer and Head of Corporate Development
Executive Vice President and Chief Commercial Officer
Executive Vice President and Chief Architect
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