DTMA & Memory Controller Design Lead
L&T Semiconductor Technologies · Posted Oct 17
Advanced fabless semiconductor chip design and power electronics solutions for automotive, industrial, and energy markets
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About the role
L&T Semiconductor Technologies (LTSCT) is building an xPU compute platform built around a 512-bank SRAM (8 TB/s) and a 6-stack HBM4e subsystem (384 GB, 12 TB/s); this role reports to the Senior Architect, DC HW Systems. The DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access engine together with HBM4e memory-controller integration, orchestrating all data movement between SRAM banks, HBM4e, and the BFOS PE arrays. The work spans micro-architecture and RTL, descriptor-based DMA and tensor-tiling mechanisms, QoS/flow-control interfaces to the NoC, and bandwidth/latency closure for AI workloads.
What you will do
- Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays.
- Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth.
- Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate).
- Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow.
- Architect the 512-bank, 8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic.
- Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency.
- Define QoS and flow-control interfaces to the NoC and compute engine to prevent stalls and starvation.
- Drive verification, performance modeling, and bandwidth/latency closure across realistic AI workload traffic.
- Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs.
Skills used in this role
What the employer is looking for
- 10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth SoCs.
- Deep expertise with DRAM/HBM controller architecture, scheduling, and timing (HBM2E/HBM3/HBM3E; HBM4e a strong plus).
- Strong RTL (SystemVerilog) design skills for DMA engines, arbiters, and memory schedulers.
- Solid understanding of multi-bank SRAM architectures, banking/interleaving, and conflict resolution.
- Experience with descriptor-based DMA, gather/scatter, tensor tiling, and prefetching.
- Knowledge of address mapping, request reordering, and bandwidth/efficiency optimization.
- Familiarity with AI/ML data-movement patterns and their impact on memory-system design.
- Hands-on performance modeling and closure for high-bandwidth memory subsystems.
- Proficiency in C/C++/Python for modeling and verification.
- Proven technical leadership and cross-functional collaboration.
Preferred qualifications
- Experience integrating HBM PHY/controller IP on advanced nodes.
- Background in AI accelerator or HPC memory subsystems.
- Familiarity with UCIe/NoC traffic interaction with memory controllers.
- M.Tech/MS in EE/ECE or equivalent.
Benefits and support
- Compensation and benefits are detailed in the job posting
About L&T Semiconductor Technologies
L&T Semiconductor Technologies (LTSCT) is a fabless semiconductor company specializing in advanced chip design, SiC and GaN power semiconductors, and sustainable technology solutions. Backed by the engineering legacy of Larsen & Toubro, the company develops high-performance power, sense, and compute semiconductor solutions tailored for automotive, industrial, and energy sectors globally.
- Industry
- Semiconductors
- Company size
- 251-500 employees
- Founded
- 2023
- Location
- Mumbai, Maharashtra, India
- Funding stage
- Corporate Subsidiary
Funding
Corporate Subsidiary · ₹859 Cr raised
Leadership
Chief Executive Officer
Rahul Nilosey
Chief Financial Officer
Sekharipuram Narayanan Subrahmanyan
Chairman
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