Director, Engineering (GPU Physical Design)
Qualcomm · Posted Oct 7
Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions
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About the role
Qualcomm's ASIC Engineering group defines, models, designs, verifies, and implements IP (block/SoC) for high-performance, low-power products, with engineers collaborating across cross-functional groups to determine product execution paths. This Director, Engineering (GPU Physical Design) role leads a team working on high-performance GPU cores, covering floor-planning, place and route, CTS, formal and physical verification, PDN, timing closure, and power optimization. The position drives PPA trade-off decisions and timing convergence for high-frequency, data-path intensive cores in the latest technology nodes.
What you will do
- Design, build, and maintain systems that power Qualcomm's semiconductors platform
- Collaborate with cross-functional teams to ship high-impact features
Skills used in this role
What the employer is looking for
- Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution
- 20+ years of experience in Physical Design/Implementation
- 10 years of experience in leading a team working on high performance cores
- Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
- Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
- Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
- Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
- Good understanding of clocking architecture.
- Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
- Well versed with Tcl/Perl Scripting
- Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
- Strong problem-solving skills and good communication skills.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Qualcomm
Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.
- Industry
- Semiconductors
- Company size
- 50000+ employees
- Founded
- 1985
- Location
- San Diego, California, USA
- Funding stage
- Public Company
Funding
Public Company · $53M raised
- 2018-11-01Grant
Leadership
President and Chief Executive Officer
Chief Financial Officer and Chief Operating Officer
James H. Thompson
Chief Technology Officer
Chief Marketing Officer
Ann Chaplin
General Counsel and Corporate Secretary
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