DFT Engineer
Arm · Posted Sep 21
Semiconductor IP, energy-efficient CPU architecture, and high-performance compute platforms
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About the role
Arm's Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within the context of a SoC, using the latest DFT techniques and process technologies. The team collaborates closely with RTL, Verification, Physical Implementation, and Test engineering teams from early investigation through tape-out and silicon test/characterization on ATE. This role will architect, implement, and validate DFT techniques on test chips and hard macros, do RTL- and gate-level DFT insertion, generate ATE test patterns, and support timing closure and silicon debug.
What you will do
- Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros.
- Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon.
- Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.
Skills used in this role
What the employer is looking for
- This role is for a DFT Engineer with proven ability of 2 to 5 years in Design for Test
- Experience coding Verilog RTL, TCL and/or Perl
- Proficient in Unix/Linux environments
- Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
- Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field
Preferred qualifications
- Familiarity with IEEE 1149, 1500, 1687, 1838
- Synthesis & Static Timing Analysis
- Familiarity with SoC style architectures including multi-clock domain and low power design practices.
- Validated understanding of Siemens DFT tools
- Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
- Experience with 2.5D and 3D test
- Ability to work both collaboratively on a team and independently
- Hard-working and excellent time management skills with an ability to multi-task
- An upbeat demeanor to working on exciting projects on the cutting edge of technology
- Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools
Benefits and support
- Hybrid working model with flexibility — teams determine their own hybrid working patterns
About Arm
Arm architects, develops, and licenses high-performance, energy-efficient CPU products and related semiconductor intellectual property. Its technology powers over 99% of the world's smartphones as well as a vast array of devices ranging from tiny sensors and wearables to cloud-scale AI supercomputers.
- Industry
- Semiconductors
- Company size
- 8000+ employees
- Founded
- 1990
- Location
- Cambridge, United Kingdom
- Funding stage
- Public Company
Funding
Public Company
- 2023-09-14IPO$5.23B
Leadership
Chief Executive Officer, Board Member
Executive Vice President and Chief Financial Officer
Executive Vice President, Chief Legal Officer and Head of Corporate Development
Executive Vice President and Chief Commercial Officer
Executive Vice President and Chief Architect
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