DFT Design Engineers
Samsung Semiconductor · Posted Oct 15
Advanced memory, foundry, system LSI, and semiconductor manufacturing solutions
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About the role
Samsung Semiconductor India Research works on industry-leading semiconductor solutions across System LSI, Memory and Foundry, including Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/6G, neural processors, serial interfaces and multimedia IPs. As one of Samsung Electronics' largest R&D centers outside Korea, the team works across diverse domains, products and emerging technology areas. This role is for an ASIC design engineer focused on DFT, coverage, timing closure and post-silicon diagnosis, including DFT architecture, scan and MBIST insertion, ATPG, and DFT timing closure.
What you will do
- Looking for bright ASIC design engineer with excellent analytical and technical skills.
- This role provides opportunity to participate in the ASIC development, with emphasis in DFT, coverage, timing closure and post-silicon diagnosis
- Experience in architecting DFT - top level test pin planning, ATPG partitioning, MBIST planning and optimization, JTAG TDR planning and integration, architecting DFT clocking schemes, EFUSE planning for memory repair
- Defining scan compression, low coverage analysis, improve test coverage for various fault models, pattern generation, simulation with SDF
- Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies
- Executed scan & MBIST insertion, ATPG and verification at full chip level
- Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts
- Generate, review and validate DFT constraints to achieve timing closure of high speed design
- Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
- Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
- Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
- Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
- Understanding of Power Estimation/Management for DFT modes is preferred
- Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
- Strong written and oral communication skills
- Good understanding of Deep Sub Micron topics and their associated issues
- Experience – 6+ Years of Experience
Skills used in this role
What the employer is looking for
- B.Tech/B.E/M.Tech/M.E
Benefits and support
- Compensation and benefits are detailed in the job posting
About Samsung Semiconductor
Samsung Semiconductor is a world leader in advanced memory technology, integrated circuits, and semiconductor foundry services. Part of Samsung Electronics, the company develops essential hardware components like DRAM, NAND flash, application processors, and sensor solutions that power global computing, mobile, and AI infrastructure. Through continuous innovation in lithography and packaging, Samsung drives technological advancements across consumer electronics and enterprise data centers.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1969
- Location
- San Jose, California, USA
- Funding stage
- Public Company
Leadership
Jinman Han
President of Foundry Business
Yong-In Park
President of System LSI Business
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