DFT Architect
AMD · Posted Oct 6
High-performance processors, graphics cards, data center solutions, and AI accelerators
Get a personal compatibility score
Add a resume for personal matches
About the role
AMD's Server CPU engineering team works on next-generation EPYC Server SoCs, ensuring testability and manufacturing quality across the design cycle. The role is focused on structural Design-for-Test implementation, ATPG, LBIST, and silicon bring-up in advanced semiconductor design flows. As a key member of the team, this engineer collaborates with architecture, RTL, physical design, and product engineering groups to deliver high-quality manufacturing test patterns and drive DFT methodology and automation improvements.
What you will do
- Collaborate with Architecture teams to understand and define DFT architecture requirements.
- Work closely with RTL Design teams to ensure compliance with DFT design methodologies, rules, and best practices.
- Partner with Physical Design teams to implement DFT structures and achieve timing closure for test logic.
- Develop and execute ATPG strategies for stuck-at, transition, and other fault models using advanced test compression techniques.
- Generate, simulate, and validate high-quality manufacturing test patterns.
- Analyze coverage results and drive design enhancements to maximize fault coverage and test quality.
- Perform debug and root-cause analysis of DFT, ATPG, and LBIST-related issues throughout the design cycle.
- Collaborate with Product Engineering teams to support manufacturing test program development and qualification.
- Support silicon bring-up, characterization, yield improvement, and production debug activities.
- Develop and maintain automation tools, scripts, and flows to improve productivity and test quality.
- Drive continuous improvements in DFT methodologies, verification strategies, and automation infrastructure.
Skills used in this role
What the employer is looking for
- Strong understanding of DFT architecture, scan design, test compression, ATPG, and LBIST methodologies.
- Hands-on experience with ATPG tools such as Siemens Tessent (Mentor TK) or equivalent.
- Experience with scan insertion, fault simulation, coverage analysis, and pattern validation.
- Good understanding of Static Timing Analysis (STA) and timing closure concepts.
- Strong debugging and problem-solving skills with the ability to identify and resolve complex design issues.
- Proficiency in scripting languages such as Perl, Python, Tcl, or Shell.
- Familiarity with ASIC/SoC development flows and semiconductor manufacturing processes.
- Excellent communication and collaboration skills with the ability to work effectively in a global cross-functional environment.
- B.E./B.Tech., M.E./M.Tech., or equivalent degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
- 5+ years of relevant DFT/ATPG experience for Senior Engineer level.
Preferred qualifications
- Experience with large-scale CPU, GPU, AI, or Server SoC products.
- Knowledge of MBIST, JTAG, Boundary Scan, IEEE 1500, IJTAG, or related DFT technologies.
- Experience supporting silicon bring-up, failure analysis, and production ramp activities.
- Exposure to Emulation, Verification, or Physical Design flows is a plus.
Benefits and support
- Compensation and benefits are detailed in the job posting
About AMD
AMD is a global semiconductor company that designs high-performance central processing units (CPUs), graphics processing units (GPUs), and adaptive processors for data centers, personal computers, gaming consoles, and embedded systems. The company specializes in advanced computing solutions and AI accelerators, positioning itself as a major leader in modern high-performance and artificial intelligence hardware. Through strategic developments and acquisitions, AMD continues to expand its ecosystem across cloud infrastructure, enterprise computing, and physical AI.
- Industry
- Semiconductors
- Company size
- 31000 employees
- Founded
- 1969-05-01
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company
- 2007-11-16Post Ipo
Leadership
Chair and Chief Executive Officer
Executive Vice President, Chief Financial Officer and Treasurer
Executive Vice President and Chief Technology Officer
Executive Vice President and Chief Commercial Officer
Executive Vice President and General Manager, Data Center Solutions Business Group
Recent coverage
Taipei Times
AMD to 'Substantially' Up Capacity: CEO2026-10-07
AMD Newsroom
AMD to Report Fiscal Third Quarter 2026 Financial Results2026-10-06
Venture Atlas
AMD Agrees to Buy World Labs for About $8.2 Billion2026-09-29