DDR PHY Senior Lead Digital Design Engineer
Qualcomm · Posted Sep 30
Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions
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About the role
Qualcomm's ASICS Engineering group defines, designs, verifies, and implements high-performance, low-power IP and SoC solutions for next-generation products. This role sits with a team building next-generation memory interface IPs, covering architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products. The engineer will work on LPDDR5/LPDDR6 and future-generation memory PHY solutions for mobile, compute, XR, automotive, and AI platforms.
What you will do
- Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.
- Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.
- Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.
- Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.
- Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.
- Create and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff.
- Implement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage.
- Work closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.
- Support pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.
- Contribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.
- LPDDR5/LPDDR6 and future-generation memory PHY solutions.
- High-performance, low-power digital architectures for mobile, compute, XR, automotive, and AI platforms.
- State-of-the-art design methodologies spanning RTL design through silicon validation.
Skills used in this role
What the employer is looking for
- Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR
- Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR
- PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
- 5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.
- Strong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.
- Hands-on experience with front-end design flows, including:
- Lint
- CDC/RDC
- Low-power verification
- Synthesis
- Static Timing Analysis (STA)
- Design-for-Test (DFT)
- Familiarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.
- Strong debugging and problem-solving skills.
- Excellent teamwork, communication, and collaboration skills with global engineering teams.
Preferred qualifications
- Experience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.
- Knowledge of UPF, power-aware design methodologies, and low-power architecture techniques.
- Familiarity with scan insertion, ATPG, and silicon debug activities.
- Exposure to post-silicon bring-up, validation, and characterization.
- Experience working across multi-functional teams, including verification, physical design, DFT, firmware, and system engineering.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Qualcomm
Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.
- Industry
- Semiconductors
- Company size
- 50000+ employees
- Founded
- 1985
- Location
- San Diego, California, USA
- Funding stage
- Public Company
Funding
Public Company · $53M raised
- 2018-11-01Grant
Leadership
President and Chief Executive Officer
Chief Financial Officer and Chief Operating Officer
James H. Thompson
Chief Technology Officer
Chief Marketing Officer
Ann Chaplin
General Counsel and Corporate Secretary
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