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ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

Qualcomm · Posted Oct 28

Semiconductor, 5G wireless technology, mobile platform, and AI computing solutions

Bangalore, IndiaFull-timeOnsiteLead/Staff3–8 years₹28.0L–₹48.0L yearly100+ applicants
SemiconductorsWireless TechnologyTelecommunicationsArtificial IntelligenceMobile ComputingPublic Company
Full time

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About the role

Qualcomm's Hardware Engineering group works on system power management IP cores and subsystem design targeted for Snapdragon SoCs across mobile, compute, IoT and Automotive markets. The role involves micro-architecture and RTL design of IP cores and subsystems, working with Systems, Verification, SoC, SW, PD and DFT teams for design convergence. The engineer also qualifies designs using static checks such as Lint, CDC and CLP, and owns synthesis, LEC and netlist CLP.

What you will do

  • Micro-architecture and RTL design for IP Cores / subsystems.
  • Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
  • Enable SW teams to use HW blocks.
  • Qualify designs using static tool checks including Lint, CDC, CLP etc.
  • Synthesis, LEC and Netlist CLP
  • Report status and communicate progress against expectations.

Skills used in this role

What the employer is looking for

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Preferred qualifications

  • 3 to 8 years of strong experience in RTL design for ASICs
  • Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains
  • Familiar with UPF and power domain crossing
  • Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
  • Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
  • Experience in low power design methodology and clock domain crossing designs
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in formal verification with Cadence LEC
  • Understanding of full RTL to GDS flow to interact with DFT and PD teams
  • Expertise in Perl/TCL/Python language
  • Experienced in database management flows with Clearcase/Clearquest.
  • Expertise in post-Si debug is a plus
  • Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members.
  • Team player, self-motivated, should be able to work with minimal supervision.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Qualcomm

Qualcomm is a global leader in the development and commercialization of foundational technologies for the wireless industry, including mobile processors, 5G, and on-device artificial intelligence. The company designs and markets digital communications products, semiconductor solutions, and system software used globally across smartphones, automotive solutions, IoT devices, and computing systems. Through extensive R&D and intellectual property licensing, Qualcomm powers a highly interconnected and smarter world.

Industry
Semiconductors
Company size
50000+ employees
Founded
1985
Location
San Diego, California, USA
Funding stage
Public Company

Funding

Public Company · $53M raised

Western Technology Investment
  • 2018-11-01Grant

Leadership

CR
Cristiano R. Amon

President and Chief Executive Officer

AP
Akash Palkhiwala

Chief Financial Officer and Chief Operating Officer

JH

James H. Thompson

Chief Technology Officer

DM
Don McGuire

Chief Marketing Officer

AC

Ann Chaplin

General Counsel and Corporate Secretary

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