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Memory Layout Design Engineer

Broadcom · Posted Oct 19

Semiconductor and infrastructure software solutions for enterprise networks and data centers

Bengaluru, India (Electronic City)Full-timeOnsiteLead/Staff10+ years₹40.0L–₹65.0L yearly<25 applicants
SemiconductorsInfrastructure SoftwareEnterprise SoftwareComputer HardwareNetworkingPublic Company
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About the role

This is a memory layout design role within Broadcom's Bangalore Electronic City site, working on physical layout for advanced submicron process nodes (7nm, 5nm, 3nm, 2nm). The work covers memory layout topology, floor-planning, hierarchy layout, chip integration, and physical verification (LVS, DRC, ERC, antenna, electromigration) using Cadence Virtuoso and Calibre tools. The engineer will manage schedules and layout floor-planning, ensure end-to-end deliverables, and coordinate with SOC and library teams while leading technology reviews and mentoring junior engineers.

What you will do

  • Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.
  • Manage scheduling, timelines, and layout floor-planning.
  • Ensure end-to-end deliverables are completed with high quality and within the planned schedule.
  • Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.

Skills used in this role

Cadence VirtuosoVirtuoso Layout XLLayout XLCadence Schematic CaptureCalibreHerculesLVSDRCERCSKILLMemory Layout DesignPhysical VerificationFloorplanningChip IntegrationLayout Automation

What the employer is looking for

  • Bachelor's degree with 12 years of experience or a Master's degree with over 10 years of experience.
  • Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
  • Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).
  • Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).
  • Experience with Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.
  • Proficiency in floor-planning, hierarchy layout, and chip integration.
  • Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
  • Ability to lead teams, train junior engineers, and manage projects effectively.
  • Strong knowledge of memory layout topology; experience with memory compilers is preferred.
  • Knowledge of AI, layout automation, and script/SKILL programming is preferred.
  • Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  • Self-reliant with the ability to work both independently and collaboratively.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Broadcom

Broadcom Inc. is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. Its products serve critical markets including data centers, networking, enterprise software, broadband, wireless, and storage. Through strategic expansions and robust R&D, Broadcom powers complex digital infrastructure worldwide.

Industry
Semiconductors
Company size
20000+ employees
Founded
1961
Location
Palo Alto, California, USA
Funding stage
Public Company

Leadership

HE
Hock E. Tan

President and Chief Executive Officer

AT

Amie Thuener

Chief Financial Officer and Principal Accounting Officer

CK

Charlie Kawwas

President, Semiconductor Solutions Group

RV

Ram Velaga

President, Infrastructure Software Group

MB

Mark Brazeal

Chief Legal and Corporate Affairs Officer

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