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Sr. Memory Layout Design Engineer

Broadcom · Posted Oct 9

Semiconductor and infrastructure software solutions for enterprise networks and data centers

Bangalore Electronic City, India (IND-Bangalore Electronic City - S1)Full-timeOnsiteSenior Level8+ years₹40.0L–₹70.0L yearly48 applicants
SemiconductorsInfrastructure SoftwareEnterprise SoftwareComputer HardwareNetworkingPublic Company
Full time

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About the role

This role sits within Broadcom's layout design team working on memory layout for advanced submicron CMOS processes (7nm, 5nm, 3nm, 2nm). The work covers memory layout design, floor-planning, hierarchy layout, chip integration, and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) using Cadence Virtuoso and Calibre tools. The engineer will own start-to-end deliverables, drive layout scripting and automation, and lead and train junior engineers on new technology reviews and layout methodologies.

What you will do

  • Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
  • Manage scheduling, timelines, and layout floor-planning.
  • Responsible for start to end deliverables with quality within the planned schedule.
  • Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
  • Able to think and help in layout scripting and automation

Skills used in this role

Cadence VirtuosoVirtuoso XLVXLEXLCalibreHerculesSKILLLVSDRCERCAntennaElectromigrationCMOSMemory LayoutStandard Cell LayoutI/O LayoutPhysical VerificationFloorplanningChip IntegrationMemory ArchitectureMemory CompilersScriptingAutomationCommunicationLeadership

What the employer is looking for

  • Minimum 8 years of experience with strong layout knowledge
  • Bachelor's degree required.
  • Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
  • Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
  • Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.
  • Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
  • Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
  • Proficiency in floor-planning, hierarchy layout, and chip integration.
  • Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
  • Knowledge of AI, automation in layout, Script Programming and SKILL Programming
  • Ability to lead, train junior engineers, and manage projects effectively.
  • Good knowledge of memory layout topology; experience with memory compilers is a plus.
  • Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  • Self-reliant with the ability to work both independently and collaboratively.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Broadcom

Broadcom Inc. is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. Its products serve critical markets including data centers, networking, enterprise software, broadband, wireless, and storage. Through strategic expansions and robust R&D, Broadcom powers complex digital infrastructure worldwide.

Industry
Semiconductors
Company size
20000+ employees
Founded
1961
Location
Palo Alto, California, USA
Funding stage
Public Company

Leadership

HE
Hock E. Tan

President and Chief Executive Officer

AT

Amie Thuener

Chief Financial Officer and Principal Accounting Officer

CK

Charlie Kawwas

President, Semiconductor Solutions Group

RV

Ram Velaga

President, Infrastructure Software Group

MB

Mark Brazeal

Chief Legal and Corporate Affairs Officer