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Technical Lead – LINT, CDC & RDC Verification

NXP Semiconductors · Posted Nov 5

High-performance mixed-signal and standard semiconductor products for automotive, industrial, and mobile applications

NoidaFull-timeHybridLead/Staff10–15 years₹40.0L–₹70.0L yearly<25 applicants
SemiconductorsHardwareAutomotiveInternet of ThingsEmbedded SystemsPublic Company
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About the role

NXP Semiconductors is hiring a verification lead to drive methodology development, qualification, deployment, and signoff for LINT, CDC, and RDC across complex SoC and IP programs. The role works with Siemens Questa and Synopsys VC SpyGlass solutions, defining enterprise-wide signoff methodologies and debugging structural verification issues. It involves collaboration with design, DFT, safety, and CAD teams, plus automation and mentoring responsibilities.

What you will do

  • Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
  • Drive deployment and qualification of EDA solutions across multiple projects.
  • Establish best practices, waiver management processes, and signoff criteria.
  • Lead technical reviews and provide guidance on structural verification issues.
  • Perform RTL quality checks using Questa Lint and VC SpyGlass Lint.
  • Analyze and resolve violations related to:
  • Coding style
  • Synthesis mismatches
  • FSM issues
  • Dead code
  • X-propagation
  • Clock/reset usage
  • DFT-related checks
  • Develop custom rule sets and methodology enhancements.
  • Execute CDC signoff using Questa CDC and VC SpyGlass CDC.
  • Analyze:
  • Clock domain crossings
  • Synchronizer structures
  • Reconvergence issues
  • Data coherency checks
  • Handshake protocol verification
  • Asynchronous interface validation
  • Drive CDC closure and root-cause analysis.
  • Lead Reset Domain Crossing analysis and signoff.
  • Debug RDC violations, reset synchronizers, reset sequencing, and metastability risks.
  • Collaborate with Design and Functional Safety teams to ensure robust reset architecture.
  • Develop Tcl/Python/Perl based automation for verification flows.
  • Improve runtime, reporting, and dashboard generation.
  • Create reusable verification infrastructure and deployment packages.
  • Support CI/CD and regression integration.
  • Work closely with Design, DFT, Safety, CAD, and EDA vendors.
  • Review tool roadmaps and evaluate new features.
  • Mentor engineers and drive technical training programs.

Skills used in this role

What the employer is looking for

  • 10-15+ Years in SoC/IP Design Verification, Signoff Methodology, and EDA Tool Deployment.
  • Strong expertise in both Siemens Questa CDC/RDC/Lint and Synopsys VC SpyGlass (Lint/CDC/RDC) solutions.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About NXP Semiconductors

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As a global semiconductor leader, the company drives innovation in automotive processing, secure connected edge systems, industrial IoT, and mobile communications infrastructure.

Industry
Semiconductors
Company size
32169 employees
Founded
2006
Location
Eindhoven, Netherlands
Funding stage
Public Company

Funding

Public Company

BlackRockFMR LLCVanguardJP Morgan Asset Management

Leadership

RS

Rafael Sotomayor

President and Chief Executive Officer

BB

Bill Betz

Executive Vice President and Chief Financial Officer

LR

Lars Reger

Executive Vice President and Chief Technology Officer

CJ

Chris Jensen

Executive Vice President and Chief People Officer

JW

Jennifer Wuamett

Executive Vice President, General Counsel, and Chief Sustainability Officer

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