Physical Design Lead
NXP Semiconductors · Posted Oct 28
High-performance mixed-signal and standard semiconductor products for automotive, industrial, and mobile applications
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About the role
NXP's physical design team delivers end-to-end implementation of complex SoCs and IPs on advanced technology nodes, driving power, performance, area, quality, and schedule goals. The role is a technical leadership position covering RTL-to-GDSII implementation, including floorplanning, place-and-route, timing closure, low-power design, and signoff. The Physical Design Lead will own large design partitions and top-level activities, drive methodology and automation improvements, and mentor engineers across multiple projects.
What you will do
- Lead and execute all aspects of physical design from RTL to GDSII, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure, physical verification, and tapeout.
- Own the complete physical implementation of complex SoC partitions, subsystems, or top-level designs and drive closure to production-quality signoff.
- Perform and drive advanced static timing analysis (STA), multi-corner multi-mode (MCMM) optimization, timing ECO implementation, and signoff closure.
- Drive closure across power, performance, area, signal integrity (SI), electromigration (EM), IR-drop, reliability, and manufacturability targets.
- Develop and optimize physical design methodologies, automation frameworks, flows, and scripts to improve design quality, efficiency, and turnaround time.
- Analyze critical timing paths, congestion, routing, and power bottlenecks, and develop innovative solutions to achieve aggressive PPA goals.
- Collaborate closely with architecture, RTL design, verification, DFT, package, and technology teams to resolve implementation challenges and optimize overall product quality.
- Drive physical signoff activities including DRC, LVS, antenna checks, density closure, metal fill verification, and tapeout readiness reviews.
- Contribute to architecture and design reviews by providing implementation-driven feedback to improve PPA and physical feasibility.
- Evaluate and deploy new EDA tools, methodologies, and advanced implementation techniques.
- Implement advanced low-power design methodologies including clock gating, power gating, multi-voltage design, retention, isolation, and UPF/CPF-based flows.
- Mentor and guide engineers, providing technical leadership and fostering engineering excellence across teams.
- Generate comprehensive implementation reports, signoff documentation, and design reviews throughout the development cycle.
Skills used in this role
What the employer is looking for
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 15+ years of ASIC/SoC physical design experience with a proven record of successful tapeouts on advanced process technologies.
- Extensive hands-on experience in synthesis, floorplanning, place and route, timing analysis, physical verification, and signoff closure.
- Proven ability to independently drive block-level, subsystem-level, and top-level implementation of complex multi-million gate SoCs, including multi-processor architectures.
- Strong expertise in one or more of the following domains: Physical Design & Implementation Synthesis & Timing Analysis
- Deep understanding of MCMM timing closure methodologies, timing constraint development, ECO implementation, and signoff flows.
- Hands-on experience with industry-standard EDA tools, including: Cadence Innovus and Tempus Synopsys Fusion Compiler, ICC2, and PrimeTime Ansys RedHawk or equivalent EM/IR analysis tools
- Strong knowledge of physical signoff methodologies including DRC, LVS, antenna checks, density validation, and metal fill closure.
- Experience with signal integrity analysis, crosstalk mitigation, electromigration (EM), and IR-drop closure.
- Strong understanding of manufacturability requirements and Design for Manufacturability (DFM) principles.
- Proficiency in Tcl scripting and working knowledge of Python and/or Perl for automation, reporting, and flow development.
- Demonstrated ability to drive multiple implementation experiments and optimize designs against challenging PPA targets.
- Experience with advanced process nodes including 16nm FinFET and below; experience in 7nm, 5nm, or more advanced technologies is a plus.
- Hands-on experience with low-power design techniques including clock gating, power gating, multi-voltage implementation, retention, isolation, and UPF/CPF methodologies.
- Demonstrated technical leadership, mentorship, and ability to drive cross-functional initiatives.
- Excellent problem-solving, analytical, debugging, communication, and stakeholder management skills.
- Ability to thrive in a fast-paced, collaborative, and globally distributed engineering environment.
Preferred qualifications
- Experience leading physical implementation and signoff for large-scale SoCs across multiple engineering sites.
- Experience developing organization-wide design methodologies, automation frameworks, and best practices.
- Strong understanding of advanced-node challenges including congestion management, variation-aware timing closure, power integrity, and reliability signoff.
- Experience evaluating and deploying next-generation EDA technologies and AI-assisted design optimization techniques.
Benefits and support
- Compensation and benefits are detailed in the job posting
About NXP Semiconductors
NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As a global semiconductor leader, the company drives innovation in automotive processing, secure connected edge systems, industrial IoT, and mobile communications infrastructure.
- Industry
- Semiconductors
- Company size
- 32169 employees
- Founded
- 2006
- Location
- Eindhoven, Netherlands
- Funding stage
- Public Company
Funding
Public Company
Leadership
Rafael Sotomayor
President and Chief Executive Officer
Bill Betz
Executive Vice President and Chief Financial Officer
Lars Reger
Executive Vice President and Chief Technology Officer
Chris Jensen
Executive Vice President and Chief People Officer
Jennifer Wuamett
Executive Vice President, General Counsel, and Chief Sustainability Officer
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