PRINCIPAL PHYSICAL VERIFICATION ENGINEER
NXP Semiconductors · Posted Oct 5
High-performance mixed-signal and standard semiconductor products for automotive, industrial, and mobile applications
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About the role
NXP's VLSI design team is seeking a Physical Verification Design Engineer to own full-chip and block-level physical verification signoff, ensuring designs meet foundry and reliability requirements. The role covers DRC, LVS, ERC, antenna, density and reliability checks, runset, deck and automation flow development, and tapeout readiness. The engineer collaborates closely with physical design, PDK, CAD, and tapeout teams, interfaces with foundry and EDA vendors, and mentors junior engineers.
What you will do
- Perform physical verification (PV) for block-level and full-chip designs, including:
- Design Rule Check (DRC)
- Layout Versus Schematic (LVS)
- Electrical Rule Check (ERC)
- Antenna, density, and reliability checks
- Drive signoff closure by identifying and resolving PV violations efficiently.
- Work with physical design and layout teams to debug and fix violations.
- Develop and maintain runsets, decks, and automation flows using industry-standard tools.
- Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
- Lead tapeout readiness reviews and ensure high-quality database delivery.
- Perform hierarchical verification and regression management.
- Participate in improving verification methodologies, runtime, and capacity optimization.
- Interface with foundry and EDA vendors to resolve tool or deck-related issues.
- Mentor junior engineers and review their work as needed.
Skills used in this role
What the employer is looking for
- Strong analytical and problem-solving ability
- Effective communication across cross-functional teams
- Ownership mindset with focus on quality and timelines
- Ability to work independently and guide team members
Preferred qualifications
- Exposure to Physical Design (PD) concepts, including:
- Floorplanning (macro placement, block shaping, congestion awareness)
- Power Delivery Network (PDN) design (power grid, IR drop considerations)
- Understanding of:
- Placement, CTS, routing flows
- PD-PV interaction and impact of layout decisions on DRC/LVS closure
- Knowledge of:
- EM/IR, latch-up, ESD reliability checks
- Multi-patterning / EUV constraints
- Experience with full-chip integration and SoC-level challenges
- Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
- Exposure to flow automation and methodology development
Benefits and support
- Compensation and benefits are detailed in the job posting
About NXP Semiconductors
NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As a global semiconductor leader, the company drives innovation in automotive processing, secure connected edge systems, industrial IoT, and mobile communications infrastructure.
- Industry
- Semiconductors
- Company size
- 32169 employees
- Founded
- 2006
- Location
- Eindhoven, Netherlands
- Funding stage
- Public Company
Funding
Public Company
Leadership
Rafael Sotomayor
President and Chief Executive Officer
Bill Betz
Executive Vice President and Chief Financial Officer
Lars Reger
Executive Vice President and Chief Technology Officer
Chris Jensen
Executive Vice President and Chief People Officer
Jennifer Wuamett
Executive Vice President, General Counsel, and Chief Sustainability Officer
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