High Speed IO Validation Engineer
NVIDIA · Posted Oct 15
Graphics processing units, artificial intelligence platforms, accelerated computing, and data center solutions
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About the role
NVIDIA's Silicon Co-Design Group takes every GPU, SoC, and CPU silicon program from first power-on to high-volume production. The team works on high-speed I/O interconnects — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — for datacenter, AI, and client silicon. This role owns characterization and qualification of those high-speed I/Os, driving validation test plans, power and margin analysis, root-cause debug across silicon, board, firmware, and driver, and validation methodology and automation improvements.
What you will do
- Own end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.
- Develop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables — left-shifting silicon failures before deployment.
- Drive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level) — analyze trade-offs across V/F, lane config, and protocol state — and feed back into design, firmware, and binning.
- Drive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver, with platform/thermal/mechanical partners when system context matters. Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream.
- Assess manufacturing and yield implications of HSIO margin distributions — identify gaps in scaling from chip to product, and feed back into binning and design.
- Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure — increase efficiency and coverage as platform complexity grows.
Skills used in this role
What the employer is looking for
- BS or MS in Electrical or Computer Engineering (or equivalent), with 3+ years in post-silicon HSIO validation, characterization, or a closely related discipline.
- Deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and the underlying SERDES architecture — equalization, link training, electrical characterization — with strong signal integrity and jitter knowledge.
- Strong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.
- Hands-on with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR), DOE/shmoo/margin-trending, and Python-based test automation — with a track record of driving cross-functional debug across chip, package, board, firmware, driver, and system teams.
Preferred qualifications
- Hands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon — link training, equalization tuning, BER margining, or compliance debug.
- Prior SERDES, mixed-signal, or analog circuit design experience — sufficient to independently form hypotheses, design Sim-to-Si correlation experiments, and propose silicon/system-side fixes during debug.
- Track record of translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization — finding marginality at die-and-board scale before it appears in the field.
- Comfortable using AI productivity tools (Claude, Copilot, or equivalent) to compress log triage, regression analysis, scripting, and reporting workflows.
Benefits and support
- Compensation and benefits are detailed in the job posting
About NVIDIA
NVIDIA Corporation is a multinational technology company that designs graphics processing units (GPUs) for the gaming and professional markets, as well as system on a chip units (SoCs) for the mobile computing and automotive market. Pioneering accelerated computing, the company has become a driving engine of modern artificial intelligence, deep learning, and data center infrastructure.
- Industry
- Semiconductors
- Company size
- 42000+ employees
- Founded
- April 5, 1993
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Funding
Public Company · $5M raised
Leadership
Founder, President and Chief Executive Officer
Executive Vice President and Chief Financial Officer
Founder and NVIDIA Fellow
Executive Vice President, Worldwide Field Operations
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