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Senior Physical Verification Engineer

NVIDIA · Posted Oct 7

Graphics processing units, artificial intelligence platforms, accelerated computing, and data center solutions

India, BengaluruFull-timeOnsiteSenior Level5+ years₹40.0L–₹70.0L yearly99 applicants
SemiconductorsArtificial IntelligenceComputer HardwareCloud ComputingPublic Company
Full time

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About the role

NVIDIA is seeking passionate, highly motivated, and creative design engineers to join a team working on industry-leading GPUs and SOCs, impacting product lines from consumer graphics to self-driving cars and artificial intelligence. The team spans the globe with a mission to push the frontiers of computing platforms. This role owns full-chip physical verification — from block-level assembly through full-chip integration and tapeout on advanced process nodes such as TSMC A16 and TSMC 3nm — including DRC, LVS and antenna signoff, 3D die stacking, and ML/LLM-powered signoff automation.

What you will do

  • In this position, you'll own physical verification for the full chip — taking designs from block-level assembly through full-chip integration and tapeout on the latest process nodes like TSMC A16 and TSMC 3nm.
  • Own full-chip physical verification signoff — DRC, LVS, antenna — across block, partition, and top levels, and drive convergence to a clean tapeout database.
  • Push the frontier of 3D die stacking and heterogeneous integration — verifying die-to-die interfaces and stitching together dies built on entirely different process nodes into a single working system.
  • Be at the leading edge of Angstrom class technology, enabling signoff for breakthroughs like Super Power Rail backside power delivery and nanosheet GAA transistors.
  • Reinvent how signoff is done with AI — building ML- and LLM-powered automation for root-cause analysis, and flow optimization.
  • Partner with the methodology and CAD/technology groups to define and deploy correct-by-construction flows that catch issues early and reduce signoff iterations.
  • Cross-functional collaboration with P&R, Timing, IR, Library team to drive design closure on time.

Skills used in this role

Physical Design VerificationDRCLVSAntennaCalibreICVEDIFCRTL2GDSIISynthesisPlace and RouteCTSTiming ConvergenceLayout ClosureVLSIPhysical ImplementationTapeoutTSMC A16TSMC 3nm3D Die StackingHeterogeneous IntegrationMachine LearningLLMproblem solving

What the employer is looking for

  • BE/BTECH/MTECH, or equivalent, with 5+ years of experience in Physical Design Verification, full chip integration and tapeouts on the latest technology nodes.
  • Strong understanding of Physical Implementation and VLSI design concepts.
  • Expertise in signoff tools like Calibre, ICV, EDI, FC.
  • Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
  • Good problem-solving skills.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About NVIDIA

NVIDIA Corporation is a multinational technology company that designs graphics processing units (GPUs) for the gaming and professional markets, as well as system on a chip units (SoCs) for the mobile computing and automotive market. Pioneering accelerated computing, the company has become a driving engine of modern artificial intelligence, deep learning, and data center infrastructure.

Industry
Semiconductors
Company size
42000+ employees
Founded
April 5, 1993
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company · $5M raised

Worldview Technology Partners

Leadership

JH
Jensen Huang

Founder, President and Chief Executive Officer

CK
Colette Kress

Executive Vice President and Chief Financial Officer

CA
Chris A. Malachowsky

Founder and NVIDIA Fellow

JP
Jay Puri

Executive Vice President, Worldwide Field Operations