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DFT Engineer - Hardware

NVIDIA · Posted Oct 8

Graphics processing units, artificial intelligence platforms, accelerated computing, and data center solutions

India, BengaluruFull-timeOnsiteMid Level2+ years₹20.0L–₹35.0L yearly52 applicants
SemiconductorsArtificial IntelligenceComputer HardwareCloud ComputingPublic Company
Full time

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About the role

NVIDIA's Design-for-Test Engineering team works on DFT architecture, verification and post-silicon validation for some of the industry's most complex semiconductor chips. The team develops creative DFT solutions spanning test modes, ATPG configurations and silicon bring-up on NVIDIA GPU-class designs. This role owns end-to-end DFT from RTL design and gate-level scan insertion through verification (JTAG, boundary scan, security mechanisms, test clocking) to silicon bring-up, and helps build and deploy DFT methodologies for next-generation products.

What you will do

  • As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
  • Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
  • In addition, you will help develop and deploy DFT methodologies for our next generation products.
  • Be apart of innovation to strive improve the quality of DFT methods.
  • You will also need to work with multi-functional teams to incorporate DFT features into the chip.
  • Occasional travel and also some late hours online meetings involved during critical milestones.

Skills used in this role

DFTRTL designscan insertionJTAGboundary scanATPGsilicon bring-upstatic timing analysisECOASICHDLdigital logic designBISTIEEE 1149.1IEEE 1500PerlPythonRTL verificationgate-level simulationproblem solving

What the employer is looking for

  • BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
  • You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
  • Experience in RTL and Gates verification and simulation.
  • You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
  • Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
  • Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

Benefits and support

  • Compensation and benefits are detailed in the job posting

About NVIDIA

NVIDIA Corporation is a multinational technology company that designs graphics processing units (GPUs) for the gaming and professional markets, as well as system on a chip units (SoCs) for the mobile computing and automotive market. Pioneering accelerated computing, the company has become a driving engine of modern artificial intelligence, deep learning, and data center infrastructure.

Industry
Semiconductors
Company size
42000+ employees
Founded
April 5, 1993
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company · $5M raised

Worldview Technology Partners

Leadership

JH
Jensen Huang

Founder, President and Chief Executive Officer

CK
Colette Kress

Executive Vice President and Chief Financial Officer

CA
Chris A. Malachowsky

Founder and NVIDIA Fellow

JP
Jay Puri

Executive Vice President, Worldwide Field Operations