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Senior Circuit Silicon Correlation DFT Engineer

NVIDIA · Posted Sep 17

Graphics processing units, artificial intelligence platforms, accelerated computing, and data center solutions

India, BengaluruFull-timeHybridSenior Level8+ years₹45.0L–₹75.0L yearly100+ applicants
SemiconductorsArtificial IntelligenceComputer HardwareCloud ComputingPublic Company
Full time

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About the role

NVIDIA has continuously reinvented itself over two decades, from inventing the GPU in 1999 to igniting modern AI with GPU deep learning. The team works on ground breaking processor design and debug in deep submicron technologies, focused on silicon characterization and correlation to pre-silicon performance and power models. This role involves generating ATPG patterns for silicon speed path debug, RTL and gate level verification, RAM correlation, and developing new DFT-based methodologies to analyze mis-correlation in logic and RAM.

What you will do

  • Participate in ground breaking Processor design and debug in deep submicron technologies.
  • Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.
  • Responsible for generating ATPG patterns for Silicon speed path debug.
  • RTL and gate level verification for ATPG, non-ATPG patterns.
  • Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.
  • RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon
  • Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run
  • Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.

Skills used in this role

DFTATPGBISTScan CompressionFault ModelsFault SimulationLogic DesignRTL VerificationGate-Level VerificationVCSTessentPythonPerlTclMakeSTARAM CharacterizationVLSICircuit DesignSilicon Characterization

What the employer is looking for

  • BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.
  • Good understanding of Design-for-test(DFT) and logic design is required.
  • Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
  • Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.
  • Experience in VLSI simulation tools like VCS etc
  • Experience with pattern generation using tools such as tessent.

Preferred qualifications

  • Basics of circuits and RAM functionality/architecture will be helpful.
  • Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.
  • Prior experience in STA and basic understanding of circuit concepts will help in the role.
  • Post-Silicon data gathering experience is a plus.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About NVIDIA

NVIDIA Corporation is a multinational technology company that designs graphics processing units (GPUs) for the gaming and professional markets, as well as system on a chip units (SoCs) for the mobile computing and automotive market. Pioneering accelerated computing, the company has become a driving engine of modern artificial intelligence, deep learning, and data center infrastructure.

Industry
Semiconductors
Company size
42000+ employees
Founded
April 5, 1993
Location
Santa Clara, California, USA
Funding stage
Public Company

Funding

Public Company · $5M raised

Worldview Technology Partners

Leadership

JH
Jensen Huang

Founder, President and Chief Executive Officer

CK
Colette Kress

Executive Vice President and Chief Financial Officer

CA
Chris A. Malachowsky

Founder and NVIDIA Fellow

JP
Jay Puri

Executive Vice President, Worldwide Field Operations